In article <u3hmu3$101jg$1@dont-email.me>, cr88192@gmail.com (BGB) wrote:

> On 5/10/2023 1:03 PM, Scott Lurndal wrote:

> > There are some which have support for A32/T32 at EL0. I've not
> > seen any that have A32 support for any higher exception level.
> > (EL0 is usermode, EL1 is kernel, EL2 is Hypervisor and EL3 is
> > machine (i.e. SMM on intel).
> >
> > There's really no reason to support AArch32 (A32/T32 encodings)
> > even at EL0 anymore.

The early 64-bit OoO cores (Cortex-A57, -72, -73 and -75) had at least
EL1 support for 32-bit. That went away in Cortex-A76.
<https://en.wikipedia.org/wiki/ARM_Cortex-A76>

32-bit is disappearing from the last couple of years' cores, though.

> > Where have you seen [fagile performance]? Specifically for ARMv8
> > and up?
> Trying to build and run code on cellphones, typically in Termux.
> Both my old and current phone have Cortex-A53 based CPUs.

I'll believe it for those in-order cores. The OoO cores are reasonably
consistent performers.

> The Raspberry Pi 3 also had similar behavior (though this is much
> less true on the Raspberry Pi 4).

That fits: the Pi 3 has Cortex-A53 cores, the Pi 4 has early OoO cores,
Cortex-A72s.

> The A73 and A75 were OoO, but are seemingly limited mostly to
> higher-end phones...

Not in the present day. Quite low-end SoCs have A7x cores since about
2020.