Read about it on
<https://www.anandtech.com/print/18871/arm-unveils-armv92-mobile-architecture-cortex-x4-a720-and-a520-64bit-exclusive>

All the new cores only support the A64 instruction set (no longer
A32/T32), which ties in with what we have been discussing recently.

The X4 is now ten-wide with 8 ALU operations, 3 branches, and 4 loads
or stores (up to 3 loads and up to 2 stores) per cycle.

The A520 now removes an ALU compared to the A510. There is no mention
of reducing the front-end width, though, so the A520 might still be
three-wide. That's an interesting deviation from common practice,
where in recent times, if in-order was used at all, it was usually at
most two-wide, and when more performance was desired (e.g., for
Intel's small cores), the designers switched to OoO.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>