https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024

My question is how big an advance is this? The article makes it look
significant, with Intel leading, but others following in a couple of
years. But it does look like a "one trick pony", in that, once you have
done this, and reaped the benefits, while the same benefits continue,
there are no further advances that come from this.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

On Friday, June 16, 2023 at 12:11:37 PM UTC-5, Stephen Fuld wrote:
> https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
>
> My question is how big an advance is this? The article makes it look
> significant, with Intel leading, but others following in a couple of
> years. But it does look like a "one trick pony", in that, once you have
> done this, and reaped the benefits, while the same benefits continue,
> there are no further advances that come from this.
<
If you read the article closely, you will see that the frontside wiring is
deposited while the transistors are on a carrier wafer, this wafer is
cleaved off and then the transistors are attached to another wafer
and more wiring is deposited.
<
Now, consider, that this second wafer is cleaved off, and a new wafer
with transistors is attached. Now we have multiple transistor levels
in a 3D arrangement--allowing as many layers of transistors as you
need (assuming yields).
<
So, no one trick pony.
<
On the other hand, in the designs I am familiar with, Power (and ground)
wiring was no more than 20% and often not a hindrance at all (the space
was already there.) In order to keep signal lines well damped, there needs
to be a local ground/power reference <wire>, so for runs that were not
speed critical we would lay out the wires as::
vdd sig1 sig2 sig3 gnd sig4 sig5 sig6 vdd
Speed critical wires were routed::
vdd sig1 ....... sig3 gnd sig4 ....... sig6 vdd
And each successive layer was at 90º to the preceding layer.
<
So, even if they get all the power and ground routed in from the back,
significant wire runs will still need vdd and gnd in the front side stack
in order to control the electrical impedance.
<
So, give a 20% maximum, and the fact you will still need vdd and gnd
on the front side stack, I would estimate an advantage no greater than
SQRT(1 + 20%) = 1 + 10%.
<
Useful; yes, ground <sic> breaking, not so much.
>
>
> --
> - Stephen Fuld
> (e-mail address disguised to prevent spam)

On 6/16/2023 11:08 AM, MitchAlsup wrote:
> On Friday, June 16, 2023 at 12:11:37 PM UTC-5, Stephen Fuld wrote:
>> https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
>>
>> My question is how big an advance is this? The article makes it look
>> significant, with Intel leading, but others following in a couple of
>> years. But it does look like a "one trick pony", in that, once you have
>> done this, and reaped the benefits, while the same benefits continue,
>> there are no further advances that come from this.
> <
> If you read the article closely, you will see that the frontside wiring is
> deposited while the transistors are on a carrier wafer, this wafer is
> cleaved off and then the transistors are attached to another wafer
> and more wiring is deposited.
> <
> Now, consider, that this second wafer is cleaved off, and a new wafer
> with transistors is attached. Now we have multiple transistor levels
> in a 3D arrangement--allowing as many layers of transistors as you
> need (assuming yields).

Interesting. It seem sort of like a multi-chip-module, or perhaps
chiplets, but arranged vertically instead of horizontally. Is that
right? If so, and you get to three or more "levels", how do you cool
the "middle" levels?

> <
> So, no one trick pony.
> <
> On the other hand, in the designs I am familiar with, Power (and ground)
> wiring was no more than 20% and often not a hindrance at all (the space
> was already there.) In order to keep signal lines well damped, there needs
> to be a local ground/power reference <wire>, so for runs that were not
> speed critical we would lay out the wires as::
> vdd sig1 sig2 sig3 gnd sig4 sig5 sig6 vdd
> Speed critical wires were routed::
> vdd sig1 ....... sig3 gnd sig4 ....... sig6 vdd
> And each successive layer was at 90º to the preceding layer.
> <
> So, even if they get all the power and ground routed in from the back,
> significant wire runs will still need vdd and gnd in the front side stack
> in order to control the electrical impedance.
> <
> So, give a 20% maximum, and the fact you will still need vdd and gnd
> on the front side stack, I would estimate an advantage no greater than
> SQRT(1 + 20%) = 1 + 10%.
> <
> Useful; yes, ground <sic> breaking, not so much.

:-)

Thanks, Mitch.

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>On 6/16/2023 11:08 AM, MitchAlsup wrote:
>> On Friday, June 16, 2023 at 12:11:37 PM UTC-5, Stephen Fuld wrote:
>>> https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
>>>
>>> My question is how big an advance is this? The article makes it look
>>> significant, with Intel leading, but others following in a couple of
>>> years. But it does look like a "one trick pony", in that, once you have
>>> done this, and reaped the benefits, while the same benefits continue,
>>> there are no further advances that come from this.
>> <
>> If you read the article closely, you will see that the frontside wiring is
>> deposited while the transistors are on a carrier wafer, this wafer is
>> cleaved off and then the transistors are attached to another wafer
>> and more wiring is deposited.
>> <
>> Now, consider, that this second wafer is cleaved off, and a new wafer
>> with transistors is attached. Now we have multiple transistor levels
>> in a 3D arrangement--allowing as many layers of transistors as you
>> need (assuming yields).
>
>Interesting. It seem sort of like a multi-chip-module, or perhaps
>chiplets, but arranged vertically instead of horizontally. Is that
>right? If so, and you get to three or more "levels", how do you cool
>the "middle" levels?

Think of it more as a sandwich, with power planes as the bread.

On 6/17/2023 9:00 AM, Scott Lurndal wrote:
> Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>> On 6/16/2023 11:08 AM, MitchAlsup wrote:
>>> On Friday, June 16, 2023 at 12:11:37 PM UTC-5, Stephen Fuld wrote:
>>>> https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
>>>>
>>>> My question is how big an advance is this? The article makes it look
>>>> significant, with Intel leading, but others following in a couple of
>>>> years. But it does look like a "one trick pony", in that, once you have
>>>> done this, and reaped the benefits, while the same benefits continue,
>>>> there are no further advances that come from this.
>>> <
>>> If you read the article closely, you will see that the frontside wiring is
>>> deposited while the transistors are on a carrier wafer, this wafer is
>>> cleaved off and then the transistors are attached to another wafer
>>> and more wiring is deposited.
>>> <
>>> Now, consider, that this second wafer is cleaved off, and a new wafer
>>> with transistors is attached. Now we have multiple transistor levels
>>> in a 3D arrangement--allowing as many layers of transistors as you
>>> need (assuming yields).
>>
>> Interesting. It seem sort of like a multi-chip-module, or perhaps
>> chiplets, but arranged vertically instead of horizontally. Is that
>> right? If so, and you get to three or more "levels", how do you cool
>> the "middle" levels?
>
> Think of it more as a sandwich, with power planes as the bread.

OK, but I think, to extend your analogy, Mitch was talking about a
"triple decker" (or, to extend even further, more levels) sandwich, that
is, with more than one level of meat. So then how do you cool the
middle (i.e. meat) levels?

--
- Stephen Fuld
(e-mail address disguised to prevent spam)

Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>On 6/17/2023 9:00 AM, Scott Lurndal wrote:
>> Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:
>>> On 6/16/2023 11:08 AM, MitchAlsup wrote:
>>>> On Friday, June 16, 2023 at 12:11:37 PM UTC-5, Stephen Fuld wrote:
>>>>> https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
>>>>>
>>>>> My question is how big an advance is this? The article makes it look
>>>>> significant, with Intel leading, but others following in a couple of
>>>>> years. But it does look like a "one trick pony", in that, once you have
>>>>> done this, and reaped the benefits, while the same benefits continue,
>>>>> there are no further advances that come from this.
>>>> <
>>>> If you read the article closely, you will see that the frontside wiring is
>>>> deposited while the transistors are on a carrier wafer, this wafer is
>>>> cleaved off and then the transistors are attached to another wafer
>>>> and more wiring is deposited.
>>>> <
>>>> Now, consider, that this second wafer is cleaved off, and a new wafer
>>>> with transistors is attached. Now we have multiple transistor levels
>>>> in a 3D arrangement--allowing as many layers of transistors as you
>>>> need (assuming yields).
>>>
>>> Interesting. It seem sort of like a multi-chip-module, or perhaps
>>> chiplets, but arranged vertically instead of horizontally. Is that
>>> right? If so, and you get to three or more "levels", how do you cool
>>> the "middle" levels?
>>
>> Think of it more as a sandwich, with power planes as the bread.
>
>OK, but I think, to extend your analogy, Mitch was talking about a
>"triple decker" (or, to extend even further, more levels) sandwich, that
>is, with more than one level of meat. So then how do you cool the
>middle (i.e. meat) levels?

Well, that's way outside my area. Speculation: conduction? vias?
The power planes will be thermally conductive, I suspect, just due
to them being mostly metal.

On Saturday, June 17, 2023 at 11:11:42 AM UTC-5, Stephen Fuld wrote:
> On 6/17/2023 9:00 AM, Scott Lurndal wrote:
> > Stephen Fuld <sf...@alumni.cmu.edu.invalid> writes:
> >> On 6/16/2023 11:08 AM, MitchAlsup wrote:
> >>> On Friday, June 16, 2023 at 12:11:37 PM UTC-5, Stephen Fuld wrote:
> >>>> https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
> >>>>
> >>>> My question is how big an advance is this? The article makes it look
> >>>> significant, with Intel leading, but others following in a couple of
> >>>> years. But it does look like a "one trick pony", in that, once you have
> >>>> done this, and reaped the benefits, while the same benefits continue,
> >>>> there are no further advances that come from this.
> >>> <
> >>> If you read the article closely, you will see that the frontside wiring is
> >>> deposited while the transistors are on a carrier wafer, this wafer is
> >>> cleaved off and then the transistors are attached to another wafer
> >>> and more wiring is deposited.
> >>> <
> >>> Now, consider, that this second wafer is cleaved off, and a new wafer
> >>> with transistors is attached. Now we have multiple transistor levels
> >>> in a 3D arrangement--allowing as many layers of transistors as you
> >>> need (assuming yields).
> >>
> >> Interesting. It seem sort of like a multi-chip-module, or perhaps
> >> chiplets, but arranged vertically instead of horizontally. Is that
> >> right? If so, and you get to three or more "levels", how do you cool
> >> the "middle" levels?
> >
> > Think of it more as a sandwich, with power planes as the bread.
> OK, but I think, to extend your analogy, Mitch was talking about a
> "triple decker" (or, to extend even further, more levels) sandwich, that
> is, with more than one level of meat. So then how do you cool the
> middle (i.e. meat) levels?
<
Same way you cool everything--diffusion--so the things in the middle
better not be consuming gobs of power. But perhaps with enough
copper in the middle layers we get some conduction to the outside.
<
> --
> - Stephen Fuld
> (e-mail address disguised to prevent spam)

Scott Lurndal <scott@slp53.sl.home> schrieb:
> Stephen Fuld <sfuld@alumni.cmu.edu.invalid> writes:

>>OK, but I think, to extend your analogy, Mitch was talking about a
>>"triple decker" (or, to extend even further, more levels) sandwich, that
>>is, with more than one level of meat. So then how do you cool the
>>middle (i.e. meat) levels?
>
> Well, that's way outside my area. Speculation: conduction? vias?
> The power planes will be thermally conductive, I suspect, just due
> to them being mostly metal.

Crystalline silicon appears to be an excellent conductor of heat,
randomly googling a few reference gives numbers for pure silicon
of 150 W/(m*K), with doped silicon having around 120 W/(m*K).

Even pure copper isn't that much better, at 400 W/(m*K).

So, there is no chane of removing a significant amount of heat along
the planes of the "sandwich", and heat dispersal will definitely
be a major concern when stacking multiple silicon wafers on top
of each other.

MitchAlsup <MitchAlsup@aol.com> schrieb:
> On Saturday, June 17, 2023 at 11:11:42 AM UTC-5, Stephen Fuld wrote:

>> OK, but I think, to extend your analogy, Mitch was talking about a
>> "triple decker" (or, to extend even further, more levels) sandwich, that
>> is, with more than one level of meat. So then how do you cool the
>> middle (i.e. meat) levels?
><
> Same way you cool everything--diffusion--so the things in the middle
> better not be consuming gobs of power. But perhaps with enough
> copper in the middle layers we get some conduction to the outside.

#ifdef PEDANTIC
Heat conduction, actually.
#endif

If you have a plate with thickness d much smaller than the other
dimensions, with an uniform inner heat dissipation rate q (in
W/m^3), with heat conductivity lambda (W/(m*K)), with both sides
at T0, then the central temperature is T_center = T0 + q * d^2 /
(8 * lambda).

So a chip of thickness 1 mm dissipating 100 W over an area of 1
cm^2 would have a heat disipation rate of 1e9 W/m^3. Given a
thermal conductivity of crystalline silicon of 120 W/(m*K),
the central temperature would be around 1.04 K larger than the
outside temperature.

Cool only one side, that would increase to 4.17 K.

For more accurate numbers, plug in real numbers for existing
chips, therse are just a very rough estimate :-)

On 6/17/23 12:11 PM, Stephen Fuld wrote:
[snip backside power early step in full 3D integration]
>> Think of it more as a sandwich, with power planes as the bread.
>
> OK, but I think, to extend your analogy, Mitch was talking about a
> "triple decker" (or, to extend even further, more levels)
> sandwich, that is, with more than one level of meat.  So then how
> do you cool the middle (i.e. meat) levels?

I seem to recall IBM doing research on tiny liquid cooling
channels. Such would obviously interfere with circuit density —
unless one could somehow transmit power through the liquid??? One
might also imagine thin-ish cooling/heat sink layers pierced by
less than maximally dense wiring.

Non-volatile memory in the inner layers may also contribute less
to heat generation compared to SRAM (leakage) or DRAM (refresh)
for less active memory, perhaps especially for read-mostly memory
(non-volatile memory tends to have more time and energy intensive
writes than reads).

Obviously, "communication bandwidth" of heat, power, and data
between the 3D integrated circuit and the outside world would also
be limited by surface area. This hints that islands of integration
may be more practical, where high density chunks are somewhat
isolated to facilitate heat transfer. Islands within an
archipelago (package) could have fairly high data bandwidth and
only moderate latency and communication power cost. Thick islands
would have more circuitry close together for faster (and less
energy-intensive) communication but relatively less surface area
for "communication" with the outside. (This seems to continue the
trend of locality and communication being increasingly important
for performance.)

On Friday, June 16, 2023 at 12:08:45 PM UTC-6, MitchAlsup wrote:
> On Friday, June 16, 2023 at 12:11:37 PM UTC-5, Stephen Fuld wrote:
> > https://www.anandtech.com/show/18894/intel-details-powervia-tech-backside-power-on-schedule-for-2024
> >
> > My question is how big an advance is this? The article makes it look
> > significant, with Intel leading, but others following in a couple of
> > years. But it does look like a "one trick pony", in that, once you have
> > done this, and reaped the benefits, while the same benefits continue,
> > there are no further advances that come from this.
> <
> If you read the article closely, you will see that the frontside wiring is
> deposited while the transistors are on a carrier wafer, this wafer is
> cleaved off and then the transistors are attached to another wafer
> and more wiring is deposited.
> <
> Now, consider, that this second wafer is cleaved off, and a new wafer
> with transistors is attached. Now we have multiple transistor levels
> in a 3D arrangement--allowing as many layers of transistors as you
> need (assuming yields).
> <
> So, no one trick pony.

Having read the article, I think that:

1) The idea of using this to attach more layers of transistors isn't
currently even being considered, and

2) That would lead to a limit of *two* layers of transistors, unless
you wanted to put all the wiring on one side of the chip.

Actually, though, Mitch, I think that *you* have just come up with
the way to keep Moore's Law running forever. Although a chip with,
say, 32 layers of transistors on *one* side, and 1024 layers of
wiring on the *other* side...

-would still have the problems with through-layer interconnects, but
in even a worse degree, that current chips have, that putting the power
wires (hey, why not throw in the clock wires) on the back was intended
to alleviate,

- and, really, technically, ought not to be considered a true "3-D" design,
even though as a "layered 2-D design" it still achieves the same fundamental
density result as true 3-D...

- did I mention cooling? Of course, someone else noted they're working
on that. And having the transistors all on one side, on the surface, not
buried under all the wires does, as sort of noted, help a lot with cooling.
Even with, say, four layers of transistors instead of just one.

In any case, too, while the article _did_, in its wording, admit that this
_was_ a "one-trick pony", its point that it was a _good_ one-trick pony:
not just Intel was working on it, but so was everyone else, *and* this
was something that pretty well *everyone* was going to have to do
(like going to vertical transistor structures like Fin-FET and GAA, or
using EUV) to progress past a certain point.

Being a good one-trick pony, and part of a succession of many one-trick
ponies, each one making its own contribution to the further advance of
semiconductors, is not a bad thing.

John Savard

On Tuesday, June 20, 2023 at 5:07:05 PM UTC-6, Quadibloc wrote:
> And having the transistors all on one side, on the surface, not
> buried under all the wires does, as sort of noted, help a lot with cooling.
> Even with, say, four layers of transistors instead of just one.

And they could perhaps push this further than I anticipate. So,
perhaps they could have even sixteen layers of transistors. And,
on top of that, put two such chips face to face (wiring side to
wiring side) for what passes for a 3-D structure these days.

That would certainly allow quite an impressive transistor count
by today's standards.

John Savard

On Tuesday, June 20, 2023 at 5:07:05 PM UTC-6, Quadibloc wrote:

> - and, really, technically, ought not to be considered a true "3-D" design,
> even though as a "layered 2-D design" it still achieves the same fundamental
> density result as true 3-D...

And the reason I say _that_ is because of the topological dependence of
all those pesky through-layer interconnects. Which, as the number of transistor
layers increase, would eventually take up all the chip area.

But _it would still be possible to design a useful chip_ even if the interconnects
took up a ridiculous fraction of the chip area like up to effectively 50% (i.e.,
something like 30%, with that 30% effectively making an additional 20% unusable)
so that wouldn't, in itself, limit the number of layers too much... not that other
factors (like cooling) wouldn't keep the number of layers to something sensible.

John Savard

It's hard to tell.

It's possible that it might turn out, for example, that nearly the
same benefits could be obtained much more cheaply, without
grinding down the chip a la SOI simply by putting power on layers
3 and 4 and clock on layer 5, with the highest-priority logic wiring
on layers 1 and 2, and all the other wiring that interconnects more
distantly separated parts of the chip on layers 6 and above - instead
of the current practice of putting clock, and then power, on the
very tippy-top layers.

And variations on this theme are possible - how about clock and
power sub-distribution on layers 3, 4, and 5, so as to keep the tall
inter-layer vias down to a reasonable number, but with the global
power and clock stuff still on the topmost layers as now?

John Savard

On Tuesday, June 20, 2023 at 6:33:48 PM UTC-5, Quadibloc wrote:
> It's hard to tell.
>
> It's possible that it might turn out, for example, that nearly the
> same benefits could be obtained much more cheaply, without
> grinding down the chip a la SOI simply by putting power on layers
> 3 and 4 and clock on layer 5, with the highest-priority logic wiring
> on layers 1 and 2, and all the other wiring that interconnects more
> distantly separated parts of the chip on layers 6 and above - instead
> of the current practice of putting clock, and then power, on the
> very tippy-top layers.
<
As you go up in the layers, the features get bigger (lower resistance).
That is why Vdd and Gnd are primarily up there (and clock too).
<
This new technology is putting Vdd and Gnd in big thick layers that
<should be//are> closer to the lower levels.
<
You can argue that one could have several high density wiring layers
followed by big thick Vdd and Gnd <and clock> layers followed by
more layers of moderate feature size, too.
<
In the final analysis, yield will determine if this is a good technology
or not.
>
> And variations on this theme are possible - how about clock and
> power sub-distribution on layers 3, 4, and 5, so as to keep the tall
> inter-layer vias down to a reasonable number, but with the global
> power and clock stuff still on the topmost layers as now?
>
> John Savard