A video about something called Forksheet Transistors was suggested
to me by YouTube. I watched the first bit of it; these transistors were
said to be a step on the road to the "ultimate" transistor.

Well, instead of eating up bandwidth with videos, I prefer to read stuff.

A web search led me to the web site of IMEC, mentioned in the video.

And so now I see the roadmap she was talking about.

First, there was the Fin-FET as an improvement on the planar transistor.

Then there were the GAA (gate-all-around) designs, which are now termed
"nanosheet transistors".

The issue the next two steps in this road are dealing with is that the NMOS
and PMOS transistors in the GAA style have to be separated by a certain
distance.

The Forksheet transistor deals with this by putting a dielectric material,
that is, a strong insulator, between one NMOS GAAFET and a PMOS
GAAFET so they can be closer together.

But the "ultimate" technology is called CFET, and here the NMOS GAAFETs
are in one layer, and the PMOS GAAFETs are in another layer.

John Savard

On Friday, June 23, 2023 at 1:02:44 PM UTC-5, Quadibloc wrote:
> A video about something called Forksheet Transistors was suggested
> to me by YouTube. I watched the first bit of it; these transistors were
> said to be a step on the road to the "ultimate" transistor.
>
> Well, instead of eating up bandwidth with videos, I prefer to read stuff.
>
> A web search led me to the web site of IMEC, mentioned in the video.
>
> And so now I see the roadmap she was talking about.
>
> First, there was the Fin-FET as an improvement on the planar transistor.
>
> Then there were the GAA (gate-all-around) designs, which are now termed
> "nanosheet transistors".
>
> The issue the next two steps in this road are dealing with is that the NMOS
> and PMOS transistors in the GAA style have to be separated by a certain
> distance.
<
This has always been an issue; at least since the 3µ days when I became exposed
to semiconductor fabrication.
>
> The Forksheet transistor deals with this by putting a dielectric material,
> that is, a strong insulator, between one NMOS GAAFET and a PMOS
> GAAFET so they can be closer together.
<
It looks like they flipped the finFETs on their side (horizontal instead of vertical.
>
> But the "ultimate" technology is called CFET, and here the NMOS GAAFETs
> are in one layer, and the PMOS GAAFETs are in another layer.
<
They have been getting close during the finFET era, as they no longer "dope"
diffusion and gate, they just insert ions into the metal gates where that ion
imparts a strong electrical field over the channel. {{Dope is applying an ion
after sputtering on the gate (polysilicon first then metal second); but now
they add the ions to the metal before sputtering it on as the gate material..}}
>
> John Savard