Mitch, can you reveal what you were going to use the second W bit for in the double REX proposal?

-Peter

On Saturday, August 12, 2023 at 2:55:42 PM UTC-5, Peter Lund wrote:
> Mitch, can you reveal what you were going to use the second W bit for in the double REX proposal?
>
> -Peter
<
If I had any insight I would be happy to divulge.
However, I do not.
<
{Enter pure speculation mode without any actual data}
<
W stands for "width"
<
{Exit pure speculation mode}

On Saturday, August 12, 2023 at 10:41:51 PM UTC+2, MitchAlsup wrote:
> On Saturday, August 12, 2023 at 2:55:42 PM UTC-5, Peter Lund wrote:
> > Mitch, can you reveal what you were going to use the second W bit for in the double REX proposal?
> >
> > -Peter
> <
> If I had any insight I would be happy to divulge.
> However, I do not.
> <
> {Enter pure speculation mode without any actual data}
> <
> W stands for "width"
> <
> {Exit pure speculation mode}

Each REX prefix has a 4-bit payload. There is an extra bit for the reg/index/base register specifiers + a bit to select 64-bit operands.

You mentioned that some people inside AMD toyed with allowing two REX prefixes per instruction. That would naturally allow for 32 registers instead of 16, but it would also give us two W bits. I am wondering what the second one would have been used for.

-Peter

On Sunday, August 13, 2023 at 3:52:38 AM UTC-4, Peter Lund wrote:
> On Saturday, August 12, 2023 at 10:41:51 PM UTC+2, MitchAlsup wrote:
> > On Saturday, August 12, 2023 at 2:55:42 PM UTC-5, Peter Lund wrote:
> > > Mitch, can you reveal what you were going to use the second W bit for in the double REX proposal?
> > >
> > > -Peter
> > <
> > If I had any insight I would be happy to divulge.
> > However, I do not.
> > <
> > {Enter pure speculation mode without any actual data}
> > <
> > W stands for "width"
> > <
> > {Exit pure speculation mode}
> Each REX prefix has a 4-bit payload. There is an extra bit for the reg/index/base register specifiers + a bit to select 64-bit operands.
>
> You mentioned that some people inside AMD toyed with allowing two REX prefixes per instruction. That would naturally allow for 32 registers instead of 16, but it would also give us two W bits. I am wondering what the second one would have been used for.
>
> -Peter

With 2 W bits they could be used to specify 8, 16, 32 or 64 bit operands. That might have been helpful.

- Tim

On 8/15/2023 9:46 AM, Timothy McCaffrey wrote:
> On Sunday, August 13, 2023 at 3:52:38 AM UTC-4, Peter Lund wrote:
>> On Saturday, August 12, 2023 at 10:41:51 PM UTC+2, MitchAlsup wrote:
>>> On Saturday, August 12, 2023 at 2:55:42 PM UTC-5, Peter Lund wrote:
>>>> Mitch, can you reveal what you were going to use the second W bit for in the double REX proposal?
>>>>
>>>> -Peter
>>> <
>>> If I had any insight I would be happy to divulge.
>>> However, I do not.
>>> <
>>> {Enter pure speculation mode without any actual data}
>>> <
>>> W stands for "width"
>>> <
>>> {Exit pure speculation mode}
>> Each REX prefix has a 4-bit payload. There is an extra bit for the reg/index/base register specifiers + a bit to select 64-bit operands.
>>
>> You mentioned that some people inside AMD toyed with allowing two REX prefixes per instruction. That would naturally allow for 32 registers instead of 16, but it would also give us two W bits. I am wondering what the second one would have been used for.
>>
>> -Peter
>
> With 2 W bits they could be used to specify 8, 16, 32 or 64 bit operands. That might have been helpful.
>

16-bit ops are unlikely to be all that useful, except for memory ops.

One other possibility could be interpreting it as "do this same
operation, but on an XMM register", say:
00: 32-bit GPR
01: 64-bit GPR
10: 64-bit XMM
11: 128-bit XMM

And/or, maybe a sub-mode which, rather than interpreting the extra bits
as more GPRs, instead bridges the GPR and XMM space:
0..15: R0..R15
16..31: XMM0..XMM15

So:
10: 64-bit XMM (Combined XMM+GPR)
11: 64-bit XMM (XMM Only)

So, one could be like, say:
ADD R8Q, XMM5
Or similar...

And thus reducing the number of MOVQ instructions or similar needed for
some types of tasks.

> - Tim

On Tuesday, August 15, 2023 at 4:46:54 PM UTC+2, Timothy McCaffrey wrote:
> With 2 W bits they could be used to specify 8, 16, 32 or 64 bit operands. That might have been helpful.

I doubt it. We can do 8/32 with the first 16 GPRs without extra prefixes (only a single REX prefix) and 8/32 with all 32 GPRs with two REX prefixes. We can do 16 with the first 16 GPRs with a size prefix + a REX prefix. Only in the case of 16-bits with all 32 GPRs would it require three prefix bytes (size prefix + 2 REX prefixes). Would it be worth it to use the second W bit to save one byte in extremely rare cases that any sane compiler will be able to avoid with the right register allocation?

I doubt it.

It could be used for something else that would only require a minor change to the encoding scheme (like the F0 map or maybe BGB's suggestion about XMM registers) and actually give a small benefit or it could be used for something more radical that entails a bigger change of the encoding scheme (so it had better be worth it) and maybe give a larger benefit.

Encoding 4 operand sizes in the two W bits really doesn't seem to be worth it.

-Peter