I was reading or watching a discussion of the changeover to RISC.
At one point, the Intel i860 was mentioned.
It was described as being a RISC with a sort of VLIW mode.

That, of course, sounds sort of like my Concertina II designs.

But it really isn't. I had, some time back, read up on the i860. Its
"VLIW mode" wasn't an attempt to try to do the sort of things
the TMSC600 does, or that the Itanium would later do.

Instead, it was just an early implementation of a *superscalar*
architecture. Modern superscalar machines just read a bunch
of instructions at a time, and automatically figure out how
many instructions the computer can execute in parallel on the
instruction units it has.

The i860 didn't have nearly as many transistors to play with.

So it offered the benefits of superscalar by offering a sort of
double-speed mode where instructions were read and executed
in pairs, with the restriction that each pair had to contain one
integer instruction and one floating-point instruction.

John Savard

On Friday, August 18, 2023 at 10:46:12 PM UTC-5, Quadibloc wrote:
> I was reading or watching a discussion of the changeover to RISC.
> At one point, the Intel i860 was mentioned.
> It was described as being a RISC with a sort of VLIW mode.
>
> That, of course, sounds sort of like my Concertina II designs.
>
> But it really isn't. I had, some time back, read up on the i860. Its
> "VLIW mode" wasn't an attempt to try to do the sort of things
> the TMSC600 does, or that the Itanium would later do.
>
> Instead, it was just an early implementation of a *superscalar*
> architecture. Modern superscalar machines just read a bunch
> of instructions at a time, and automatically figure out how
> many instructions the computer can execute in parallel on the
> instruction units it has.
<
Quoting from the wikipedia entry::
<
On paper, performance was impressive for a single-chip solution; however, real-world performance was anything but. One problem, perhaps unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to order instructions properly at compile time. ..... The later Itanium architecture, also a VLIW design, suffered again from the problem of compilers incapable of delivering sufficiently optimized code.
AND
Another serious problem was the lack of any solution to handle context switching quickly. The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill them and require them all to be re-loaded. This took 62 cycles in the best case, and almost 2000 cycles in the worst. The latter is 1/20000th of a second at 40 MHz (50 microseconds), an eternity for a CPU. This largely eliminated the i860 as a general purpose CPU.
>
> The i860 didn't have nearly as many transistors to play with.
<
It had 1M transistors compared to Mc 88100 with only 165,000.
>
> So it offered the benefits of superscalar by offering a sort of
> double-speed mode where instructions were read and executed
> in pairs, with the restriction that each pair had to contain one
> integer instruction and one floating-point instruction.
<
Don't allow your design to fall into those traps.
>
> John Savard

On Sunday, August 20, 2023 at 1:42:44 AM UTC+3, MitchAlsup wrote:
> On Friday, August 18, 2023 at 10:46:12 PM UTC-5, Quadibloc wrote:
> > I was reading or watching a discussion of the changeover to RISC.
> > At one point, the Intel i860 was mentioned.
> > It was described as being a RISC with a sort of VLIW mode.
> >
> > That, of course, sounds sort of like my Concertina II designs.
> >
> > But it really isn't. I had, some time back, read up on the i860. Its
> > "VLIW mode" wasn't an attempt to try to do the sort of things
> > the TMSC600 does, or that the Itanium would later do.
> >
> > Instead, it was just an early implementation of a *superscalar*
> > architecture. Modern superscalar machines just read a bunch
> > of instructions at a time, and automatically figure out how
> > many instructions the computer can execute in parallel on the
> > instruction units it has.
> <
> Quoting from the wikipedia entry::
> <
> On paper, performance was impressive for a single-chip solution; however, real-world performance was anything but. One problem, perhaps unrecognized at the time, was that runtime code paths are difficult to predict, meaning that it becomes exceedingly difficult to order instructions properly at compile time. ..... The later Itanium architecture, also a VLIW design, suffered again from the problem of compilers incapable of delivering sufficiently optimized code.
> AND
> Another serious problem was the lack of any solution to handle context switching quickly. The i860 had several pipelines (for the ALU and FPU parts) and an interrupt could spill them and require them all to be re-loaded. This took 62 cycles in the best case, and almost 2000 cycles in the worst. The latter is 1/20000th of a second at 40 MHz (50 microseconds), an eternity for a CPU. This largely eliminated the i860 as a general purpose CPU.
> >
> > The i860 didn't have nearly as many transistors to play with.
> <
> It had 1M transistors compared to Mc 88100 with only 165,000.

That's not apple-to-apple comparison.
Mc 88100 had caches and MMU off chip. i860 had them on chip.
Caches alone were probably 70% of transistors budget.

Also, according to my understanding, i860 had separate fully-pipelined
double-precision FMUL and FADD. I don't remember details of Mc 88100 FPU.

Dual-issue mode of i860 looks to me like [failed] attempt to match
anemic front end with overgrown execution part of the core.

> >
> > So it offered the benefits of superscalar by offering a sort of
> > double-speed mode where instructions were read and executed
> > in pairs, with the restriction that each pair had to contain one
> > integer instruction and one floating-point instruction.
> <
> Don't allow your design to fall into those traps.
> >
> > John Savard

On Saturday, August 19, 2023 at 6:46:12 AM UTC+3, Quadibloc wrote:
> I was reading or watching a discussion of the changeover to RISC.
> At one point, the Intel i860 was mentioned.
> It was described as being a RISC with a sort of VLIW mode.
>
> That, of course, sounds sort of like my Concertina II designs.
>
> But it really isn't. I had, some time back, read up on the i860. Its
> "VLIW mode" wasn't an attempt to try to do the sort of things
> the TMSC600

That's rather un-orthodox spelling of TMS320C60.

> does, or that the Itanium would later do.
>
> Instead, it was just an early implementation of a *superscalar*
> architecture. Modern superscalar machines just read a bunch
> of instructions at a time, and automatically figure out how
> many instructions the computer can execute in parallel on the
> instruction units it has.
>
> The i860 didn't have nearly as many transistors to play with.
>
> So it offered the benefits of superscalar by offering a sort of
> double-speed mode where instructions were read and executed
> in pairs, with the restriction that each pair had to contain one
> integer instruction and one floating-point instruction.
>
> John Savard

What you describe sounds like Intel Pentium or DEC Alpha Ev4.
IIRC, dual-issue mode of i860 was way more weird and restrictive.
To the point that in this mode with improperly issued sequence
you could suffer not just slow execution, but wrong result.

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