Recently, in a discussion on another newsgroup, I learned that a
solar storm took place in the first few days of April 1972 which
a recent scientific paper has claimed was comparable in magnitude
to the Carrington Event.

One thing that _didn't_ happen in April 1972 was all the HP 35 calculators
out there - it had just been announced in February 1972, and I presume
a few were already delivered by this time - winding up fried.

As a result of this, I tried to look up information as to what integrated
circuit process was used for the chips in the HP 35. It turns out they
were PMOS, made in a 10 micron process, as best I could determine.

So 10 micron chips can survive a Carrington event, and we won't have
to go all the way back to vacuum tubes!

In learning about the technology of the 10 micron era, I learned that
the chips then were designed using an innovation called "four-phase
logic". This involved using four clock phases, in two non-overlapping
pairs, and making use of the capacitance of the interconnects between
transistors to effectively turn those interconnects into a buffer stage.

This technique was claimed to allow a 10x improvement in the speed
and density of circuits, as well as reducing their power consumption by
a factor of ten! So it was as beneficial as three generations of process
shrinks!

The inventor of this technique worked for Autonetics.

A start-up computer company called itself Four-Phase Systems to
celebrate the technology that let them put an eight-bit wide bit slice
chip on a single die, which chip they only used internally to make
the computer they sold, the Four Phase Systems Mark IV/70.

It had a 24-bit word.

It had hardware floating-point.

To avoid having to use special circuitry for floating-point, it used
a full 24-bit word for the exponent in both two-word single precision
and three-word double precision, allowing an exponent range of
ten to the plus or minus 2,525,233rd power.

Shades of the RECOMP II, which pulled the same trick with its
40-bit word. So a computer made possible by one Autonetics
innovation also copied an idea from a much earlier computer
from the same company!

John Savard

On 10/13/23 10:27 AM, Quadibloc wrote:
> So 10 micron chips can survive a Carrington event, and we won't have
> to go all the way back to vacuum tubes!

The voltages generated by that sort of event are measured in
volts/kilometer so a 10u chip is safe.

--
http://davesrocketworks.com
David Schultz

Quadibloc wrote:
> Recently, in a discussion on another newsgroup, I learned that a
> solar storm took place in the first few days of April 1972 which
> a recent scientific paper has claimed was comparable in magnitude
> to the Carrington Event.
>
> One thing that _didn't_ happen in April 1972 was all the HP 35 calculators
> out there - it had just been announced in February 1972, and I presume
> a few were already delivered by this time - winding up fried.
>
> As a result of this, I tried to look up information as to what integrated
> circuit process was used for the chips in the HP 35. It turns out they
> were PMOS, made in a 10 micron process, as best I could determine.

Blast from the past...

HP Journal Jun-1972 HP 35 Calculator
https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1972-06.pdf

> So 10 micron chips can survive a Carrington event, and we won't have
> to go all the way back to vacuum tubes!

A coronal mass ejection hitting the earths magnetic field can cause it to
slowly wobble, and a varying magnetic field induces currents in long wires,
and in the ground which can cause burn-out in high voltage transformers.
Its a fairly long wavelength dB/dt, measured in minutes.

https://en.wikipedia.org/wiki/Geomagnetically_induced_current

The calculator wires are too short to be susceptible.
Even an EMP from a nuke might not fry a mos calculator.

https://en.wikipedia.org/wiki/Nuclear_electromagnetic_pulse#On_small_electronics