Haker reverse engineered Apple libraties, and by trial and error,
figured out instuction.
Latency is 1.4ns per instuction, moving between registers
is 0.35ns, load 512 bita is 3.5 ns store 512 bits
is 26ns. load and store of 1024 bits requirew 128
bytes alignment, so it's not that practical.
documentation is here:
https://github.com/corsix/amx/blob/main/Instructions.md
my implementetation is here: https://github.com/bmaxa/AppleAmx/tree/main
matrix operations: https://github.com/bmaxa/matrix
you have 8 X registers, as rows, 8 Y registers as columns,
and 64 Z registers as result. Each is 8*64 bits.
I invented name of instrucions, so look at implementation
and documentation to figure out...
Intel added this instructions in january 2023, and Xeons only,
but Apple added them in 2020 on every ARM processor...

--

7-77-777, Evil Sinner!
https://www.linkedin.com/in/branimir-maksimovic-6762bbaa/

Branimir Maksimovic <branimir.maksimovic@icloud.com> writes:
>Haker reverse engineered Apple libraties, and by trial and error,
>figured out instuction.
>Latency is 1.4ns per instuction, moving between registers
>is 0.35ns, load 512 bita is 3.5 ns store 512 bits
>is 26ns. load and store of 1024 bits requirew 128
>bytes alignment, so it's not that practical.
>documentation is here:
>https://github.com/corsix/amx/blob/main/Instructions.md
>my implementetation is here: https://github.com/bmaxa/AppleAmx/tree/main
>matrix operations: https://github.com/bmaxa/matrix
>you have 8 X registers, as rows, 8 Y registers as columns,
>and 64 Z registers as result. Each is 8*64 bits.
>I invented name of instrucions, so look at implementation
>and documentation to figure out...
>Intel added this instructions in january 2023, and Xeons only,
>but Apple added them in 2020 on every ARM processor...

I wonder if they'll switch to SME in a future processor.

https://developer.arm.com/documentation/ddi0616/latest/

On 2023-10-21, Scott Lurndal <scott@slp53.sl.home> wrote:
> Branimir Maksimovic <branimir.maksimovic@icloud.com> writes:
>>Haker reverse engineered Apple libraties, and by trial and error, figured out
>>instuction. Latency is 1.4ns per instuction, moving between registers is
>>0.35ns, load 512 bita is 3.5 ns store 512 bits is 26ns. load and store of
>>1024 bits requirew 128 bytes alignment, so it's not that practical.
>>documentation is here:
>>https://github.com/corsix/amx/blob/main/Instructions.md my implementetation
>>is here: https://github.com/bmaxa/AppleAmx/tree/main matrix operations:
>>https://github.com/bmaxa/matrix you have 8 X registers, as rows, 8 Y
>>registers as columns, and 64 Z registers as result. Each is 8*64 bits. I
>>invented name of instrucions, so look at implementation and documentation to
>>figure out... Intel added this instructions in january 2023, and Xeons only,
>>but Apple added them in 2020 on every ARM processor...
>
> I wonder if they'll switch to SME in a future processor.
>
> https://developer.arm.com/documentation/ddi0616/latest/
I guess, when they make transition to ARM v9.
These M1/M2 are proper ARM v8. AMX doesn't have neither compiler
or assembler support, so they are free to make changes as
they will...

--

7-77-777, Evil Sinner!
https://www.linkedin.com/in/branimir-maksimovic-6762bbaa/