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devel / comp.arch / Re: Concertina II... again?

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o Re: Concertina II... again?Quadibloc

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Re: Concertina II... again?

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Subject: Re: Concertina II... again?
From: jsavard@ecn.ab.ca (Quadibloc)
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 by: Quadibloc - Tue, 31 Oct 2023 05:05 UTC

On Friday, March 3, 2023 at 8:42:51 AM UTC-7, MitchAlsup wrote:

> I feel that you are frustrated that you can't have your cake and eat it too.

Very definitely. So I have gone to a great deal of effort to squeeze the
opcode space so as to minimize the unavoidable compromises that come
from trying to have a full set of CISC addressing modes, plus banks of 32
registers as in a RISC architecture, with 32-bit instructions.

The reasons why I use block headers:

- to allow switching from the plain RISC decoding of every single instruction
being exactly 32 bits long to allowing use of variable-length encodings while
still allowing instructions to be decoded in parallel (just decode the header
first, and you _immediately_ know where every instruction in the block is;

Yes, I know that it's possible to decode variable-length instructions quickly
enough so that the benefits of this may be illusory;

- to allow immediate values to be used of every type and size without that
burdening the scheme for decoding the lengths of instructions with excessive
complexity.

Now, the point you made about a header being optimum for one implementation
is certainly a concern to me. I did believe that this was perhaps the greatest flaw
in the Itanium.

However, while the header format is indeed complicated, it still avoids one aspect
of the complexity of the Itanium. The block format is still simple like that of the
Texas Instruments DSP chips - all the instructions, except for the header, are the
same in any block.

So the ISA is still capable of a wide variety of implementations. It does not have
to be implemented in an 8-wide fashion. It can be implemented on a chip that
fetches and decodes 32 instruction bits at a time, or one that fetches and decodes
128 bits at a time.

Or 512 bits at a time, although there provision has to be made for imposing serialization
between the two halves.

My goal has very definitely been to design an ISA that permits implementations
in a wide variety of sizes, just like the IBM System/360. I don't achieve this quite as
well, but then the smaller sizes aren't used as much these days.

John Savard

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