First time posting here, though I have perused quite a few threads on
this mailing list over the last few weeks!

I am having some fun teaching myself CPU design (the good old "what I
cannot create, I do not understand"!). For now, I am toying around with
a Xilinx FPGA board. I've implemented a small in-order, pipelined RV32IM
core (I know, baby steps!).

I now would like to understand OoO execution better--so I started
looking at Tomasulo's algorithm. While researching the topic, I stumbled
upon a bunch of discussions here regarding CDC 6600-style scoreboards,
and how they might provide an alternative path towards building an OoO
core with multiple-issue, precise exceptions, etc. Most lecture
notes/textbooks I have found don't seem to have anything on the topic.

I have found the following references so far:
- Design of a computer from Thornton. The book is quite fascinating,
though it's taking me a while to get used to the notation.
- The source code of Libre SoC. I am rather unfamiliar with nmigen
but even then, it looks quite readable.
- A number of threads on this mailing list as well as internal
discussions on the Libre SoC website/mailing list.

Quite a few of these make direct references to book chapters from an
unpublished book by Mitch Alsup--I was wondering if there was any way to
get a copy?

Also, are there any other resources that I missed and that you would
recommend for anyone getting interested in this topic?

Thomas

On 2023-11-11 3:00 p.m., Thomas Gregoire wrote:
> First time posting here, though I have perused quite a few threads on
> this mailing list over the last few weeks!
>
> I am having some fun teaching myself CPU design (the good old "what I
> cannot create, I do not understand"!). For now, I am toying around with
> a Xilinx FPGA board. I've implemented a small in-order, pipelined RV32IM
> core (I know, baby steps!).
>
> I now would like to understand OoO execution better--so I started
> looking at Tomasulo's algorithm. While researching the topic, I stumbled
> upon a bunch of discussions here regarding CDC 6600-style scoreboards,
> and how they might provide an alternative path towards building an OoO
> core with multiple-issue, precise exceptions, etc. Most lecture
> notes/textbooks I have found don't seem to have anything on the topic.
>
> I have found the following references so far:
>   -  Design of a computer from Thornton. The book is quite fascinating,
> though it's taking me a while to get used to the notation.
>   -  The source code of Libre SoC. I am rather unfamiliar with nmigen
> but even then, it looks quite readable.
>   -  A number of threads on this mailing list as well as internal
> discussions on the Libre SoC website/mailing list.
>
> Quite a few of these make direct references to book chapters from an
> unpublished book by Mitch Alsup--I was wondering if there was any way to
> get a copy?
>
> Also, are there any other resources that I missed and that you would
> recommend for anyone getting interested in this topic?
>
> Thomas

As an example, I believe the Nyuzi core has code for a scoreboard
implementation.

https://github.com/jbush001/NyuziProcessor

I think it is a 4-thread barrel processor.

This is my first post using Thunderbird.

Thomas Gregoire wrote:

> First time posting here, though I have perused quite a few threads on
> this mailing list over the last few weeks!

> I am having some fun teaching myself CPU design (the good old "what I
> cannot create, I do not understand"!). For now, I am toying around with
> a Xilinx FPGA board. I've implemented a small in-order, pipelined RV32IM
> core (I know, baby steps!).

> I now would like to understand OoO execution better--so I started
> looking at Tomasulo's algorithm. While researching the topic, I stumbled
> upon a bunch of discussions here regarding CDC 6600-style scoreboards,
> and how they might provide an alternative path towards building an OoO
> core with multiple-issue, precise exceptions, etc. Most lecture
> notes/textbooks I have found don't seem to have anything on the topic.

> I have found the following references so far:
> - Design of a computer from Thornton. The book is quite fascinating,
> though it's taking me a while to get used to the notation.
> - The source code of Libre SoC. I am rather unfamiliar with nmigen
> but even then, it looks quite readable.
> - A number of threads on this mailing list as well as internal
> discussions on the Libre SoC website/mailing list.

> Quite a few of these make direct references to book chapters from an
> unpublished book by Mitch Alsup--I was wondering if there was any way to
> get a copy?
<
You could ask for it.
<
> Also, are there any other resources that I missed and that you would
> recommend for anyone getting interested in this topic?
<
Basically, when you get down to the nitty gritty, a Scoreboard and a
<set of> reservation stations can be made to pretty much minick each
other. The RS-style uses "tags" to denote who is broadcasting results
and the stations look at all the tags and decide which instructions
can be launched next cycle. A SB, simple decodes the tags at the sending
end and ORs them into a single tag-vector.
<
Luke and I discussed this is our previous threads.
<
RS stations have the property that each station has to be able to
look at all the tags every cycle. A SB has to look at all the wires
of the tag-vector each cycle. The tag-vector operates at lower power
than the <set of> tag busses. The RS load grows linearly with the size
of the execution window, the SB grows quadratically. So the SB is better
when the number of waiting events (launches) is smaller.
<
But the SB has other properties, that we don't use today because we
have the resources to do register renaming. A SB in a renamed register
environment is essentially NO DIFFERENT in capabilities than a RS.
<
Right now, I prefer RS for instruction data flow and SB for memory
data flow.
<
> Thomas

On 11/11/23 5:08 PM, Robert Finch wrote:
> As an example, I believe the Nyuzi core has code for a scoreboard
> implementation.
>
> https://github.com/jbush001/NyuziProcessor
>
> I think it is a 4-thread barrel processor.

Thanks a lot, Robert! It looks quite well documented, I will take a look.

On 11/11/23 6:08 PM, MitchAlsup wrote:
> You could ask for it.

I reached out in private, let me know if you didn't receive my message!

Thomas Gregoire wrote:

> On 11/11/23 6:08 PM, MitchAlsup wrote:
>> You could ask for it.

> I reached out in private, let me know if you didn't receive my message!

As of this morning, It has no9t arrived.

On 11/12/23 1:54 PM, MitchAlsup wrote:
> As of this morning, It has no9t arrived.

Odd! I've sent you another one tonight--the reply address to you from
this newsgroup seems to tie out with your LinkedIn profile, could I have
ended up in your spam folder by any chance?

Try:: MitchAlsup@aol.com

On 2023-11-11 23:08, Robert Finch wrote:
> On 2023-11-11 3:00 p.m., Thomas Gregoire wrote:

[snip]

>> Also, are there any other resources that I missed and that you would
>> recommend for anyone getting interested in this topic?
>>
>> Thomas
>
> As an example, I believe the Nyuzi core has code for a scoreboard
> implementation.
>
> https://github.com/jbush001/NyuziProcessor
>
> I think it is a 4-thread barrel processor.
Thanks for the reference! The Nyuzi processor actually appears to have
many similarities to my own MRISC32, at least at the ISA level (even
though they have quite different goals), e.g:

* 32 scalar registers and 32 vector registers
* Vector registers have 16 elements (MRISC32 has 16 *or more*)
* Each scalar register or vector lane is 32-bits wide
* How they are interpreted [int or float] is based on the instruction
* Instructions are 32-bit fixed length
* Operand configurations (Nyuzi encodes w 3 bits, MRISC32 w 2 bits):
- Scalar, scalar, scalar
- Vector, vector, scalar
- Vector, vector, vector

Nyuzi has come further with predication and masking than MRISC32,
though.

Will have to look into it some more.

/Marcus