I have now chosen between Concertina II, Concertina III, and Concertina IV.

Concertina IV will be the basis of the new Concertina II. But it will recieve
some changes.

The biggest change will be in the format of 16-bit instructions. Given there
was an objection to the format allowing two registers to be from the same
group of 8, instead the format will be

0
Opcode (5 bits)
destination register (5 bits)
source register (5 bits)

Only one integer type and two floating types will be able to be used in 16-bit
instructions.

Also, some additional header types will be added. So, while one does not need
a header to write programs with instructions with different lengths, one can
add a header to speed decoding by indicating where each instruction starts.

Also, it will be mentioned that one can write code consisting of only 32-bit
instructions and pairs of 16-bit instructions, all in 32-bit alignment, and
such code may execute faster on some implementations.

So this will combine properties of the other versions of Concertina II even
with Concertina IV as the basis.

John Savard

The revised Concertina IV, now called Concertina II, is still at

http://www.quadibloc.com/arch/ct20int.htm

John Savard

Quadibloc wrote:

> The revised Concertina IV, now called Concertina II, is still at

May I suggest that this is a poor choice (reusing a name for something
that has been substantially changed. We may get into a discussion and
misuse one name for the other adding confusion rather than illumination.

> http://www.quadibloc.com/arch/ct20int.htm

> John Savard

On Fri, 09 Feb 2024 20:56:59 +0000, MitchAlsup1 wrote:

> May I suggest that this is a poor choice (reusing a name for something
> that has been substantially changed.

That is a sound general principle. At the moment, though, what I've
been engaged in is developing a suitable candidate ISA for the Concertina
II designation. When I make a change, the older one doesn't stay on my
web site.

So I don't have a pile of earlier versions around to look at and discuss.

John Savard

Quadibloc wrote:

> On Fri, 09 Feb 2024 20:56:59 +0000, MitchAlsup1 wrote:

>> May I suggest that this is a poor choice (reusing a name for something
>> that has been substantially changed.

> That is a sound general principle. At the moment, though, what I've
> been engaged in is developing a suitable candidate ISA for the Concertina
> II designation. When I make a change, the older one doesn't stay on my
> web site.

I have done mostly the same with My 66000, however it is on revision 31.
I have a clean trail of older documents. But my ISA has changed a lot less
than yours.

> So I don't have a pile of earlier versions around to look at and discuss.

You should if you ever want to patent any of the ideas.

> John Savard

On Sat, 10 Feb 2024 18:46:32 +0000, MitchAlsup1 wrote:
> Quadibloc wrote:

>> So I don't have a pile of earlier versions around to look at and discuss.
>
> You should if you ever want to patent any of the ideas.

That, too, is a very good point. However, Concertina II doesn't
really embody anything in the way of original ideas. It's a very
conventional architecture, only using techniques that have been
tried before.

John Savard

Quadibloc wrote:

> On Sat, 10 Feb 2024 18:46:32 +0000, MitchAlsup1 wrote:
>> Quadibloc wrote:

>>> So I don't have a pile of earlier versions around to look at and discuss.
>>
>> You should if you ever want to patent any of the ideas.

> That, too, is a very good point. However, Concertina II doesn't
> really embody anything in the way of original ideas. It's a very
> conventional architecture, only using techniques that have been
> tried before.

The very fact that you packed everything everybody ever did into
one ISA is novel and passes the "If it is so obvious, why did nobody
every do it before" test.

> John Savard

On 2/10/2024 2:00 PM, MitchAlsup1 wrote:
> Quadibloc wrote:
>
>> On Sat, 10 Feb 2024 18:46:32 +0000, MitchAlsup1 wrote:
>>> Quadibloc wrote:
>
>>>> So I don't have a pile of earlier versions around to look at and
>>>> discuss.
>>>
>>> You should if you ever want to patent any of the ideas.
>
>> That, too, is a very good point. However, Concertina II doesn't
>> really embody anything in the way of original ideas. It's a very
>> conventional architecture, only using techniques that have been
>> tried before.
>
> The very fact that you packed everything everybody ever did into
> one ISA is novel and passes the "If it is so obvious, why did nobody
> every do it before" test.
>

Now, as for whether it makes sense to pack everything everyone ever did
into a single ISA actually makes sense... Yeah, about that...

Meanwhile, I have gone and decided to try and "bite the bullet" and
implement support for superscalar (thus far, solely for RV64 mode; *1).

Actually implementing it in Verilog wasn't too hard...
But, still need to see if it isn't too expensive and doesn't blow out
timing constraints.

OK, seems so far so good; Vivado has survived...

*1: RV64 will benefit more from superscalar, given for BJX2 the WEXifier
in my compiler will serve this role, and there is relatively little that
superscalar would catch that the WEXifier had missed (though, I can tell
from modeling it in the emulator, that there are a non-zero number of
cases that the WEXifier does miss; such as cases where the would-be
bundle straddles a label or similar).

Though, it appears that with the latency-reducing optimization (1-cycle
ADD and 2-cycle aligned Load), and superscalar support, then RV64G does
manage to outperform BJX2 when it comes to Dhrystone (88k vs 79k).

Software Quake performance is pretty close to break-even.
Doom is still faster with BJX2.

This was not entirely unexpected, though I didn't previously expect to
actually implement superscalar support for RISC-V. Though, can note that
RISC-V's encoding does seem to be laid out in a way that make it fairly
easy to implement superscalar checks (I am guessing this is probably
something the ISA designers prioritized).

Adding similar logic for BJX2 would likely be a little more involved:
The handling of register IDs is somewhat less consistent;
Some instructions use implicit registers;
This would need to be dealt with.

And/or take a more conservative interpretation and live with a lot of
cases potentially being missed.

Though, a fairly similar mechanism could likely be used for BJX2 as
well, just probably with some restructuring of some of the logic to deal
with it being applied to both ISAs.

Also debatable if worthwhile given the WEXifier mostly already deals
with all this...

Even if it may miss cases, and works under the assumption of the
compiler knowing what the pipeline will allow.

Then again, I guess maybe it is possible that explicitly marking which
instructions may execute in parallel is, ultimately, kinda moot. It
appears maybe I may have somewhat overestimated the costs of the "check
instruction blocks and flag which ones are safe" and "check source and
destination registers for conflict" logic.

In this case, it may well, in fact, make sense to go the conventional
RISC route of not flagging which instructions to execute in parallel.

On Sat, 10 Feb 2024 20:00:06 +0000, MitchAlsup1 wrote:

> The very fact that you packed everything everybody ever did into
> one ISA is novel and passes the "If it is so obvious, why did nobody
> every do it before" test.

At first, I thought that you were talking about the original
Concertina ISA, which indeed tried to pack almost everything anyone
ever did before into a single ISA.

Aside from whether or not doing that is of any utility, instruction
sets have been small and large in the past, so making an instruction
set larger seems too vague to be patentable.

However, on further thought, I saw that in Concertina II, because
I tried to pack a number of different things into it, there was a
potentially patentable invention lurking.

I live in Canada; in the United States, an invention can be patented
within a year of its first disclosure, but most countries have a
stricter standard than that. And Concertina II has been around for
more than a year, and this invention has been part of it from the
start, so I think I'm out of luck.

The invention?

Here's a description worded in mild patentese...

Prior art includes a number of computer designs referred to as
of the Very Long Instruction Word (VLIW) type. Initially, this
referred to architectures such as the Control Data Cyber 203
computer, where a single instruction controlled the actions of
a large number of arithmetic units; later, it came to refer to
computers such as the TMS320C6000 chip from Texas Instruments,
where a block of RISC-like instructions also included, as part
of each instruction, a bit indicating if a given instruction
could be executed in parallel with one or more of the instructions
in the block which preceded it.

The Itanium from Intel, although not designated as VLIW, used
a technique similar to that of the TMS320C6000. In its case,
a 128-bit block consisted of five indicator bits and three
instructions, each 41 bits in length; the indicator bits, among
other things, indicated which of the instructions could execute
in parallel.

The subject of the invention is a novel class of instruction set
architectures where:

The instruction set consists of a set of instructions, all of the
same length, which are in themselves complete for allowing programs
of any type to be written, but which may also be augmented by
additional instructions of other lengths;

The instructions, although identical in each position, are noted as
being organized into blocks of a certain number (most usually a
power of two) of instructiions;

A portion of the opcode space of the instructions of the standard
length is reserved for use as block headers, which may only appear
in the first position within a block.

This model may be extended by allowing headers longer than a
single instruction, or by allowing multiple headers in the first
few positions in a block.

The primary use of the header is to optionally allow the indication
of which instructions, within a block, may be executed in parallel
with those that precede them.

Other header functions are possible, such as specifying instruction
predication, also a characteristic associated with embedded processor
designs and VLIW processor designs, or extending the instruction set
while avoiding the need for mode bits that change instruction
interpretation, and which are a potential security hazard if malware
can force execution of code with them set wrongly.

It is intended that an ISA in which specifying an indication of
instruction parallelism is possible but yet optional will be of
use in permitting the use of the same instruction set across a
range of implementations:

Simple implementations, in which the indication of parallelism
is ignored, as they can only execute a single instruction at a
time;

Intermediate implementations, with pipelining and superscalar
capabilities, which make use of the indications of parallelism,
if present, to permit more efficient execution of programs;

Large implementations, which include interlocks and out-of-order
execution, which are able to determine the optimum manner to
execute the instructions in an instruction stream without the
need for an explicit indication of parallelism.

Well-formed programs, where the indication of parallelism, if
given with the program, is correct, in that instructions indicated
as being capable of being executed in parallel may indeed do so
without disturbing each other's results, would execute compatibly
on all three classes of implementation.

Programs with errors in their indication of parallelism would still
execute correctly on the first and third classes of implementation;
they would produce incorrect results on lightweight intermediate
implementations, but an intermediate implementation could be given
additional interlock circuitry to enable it to be fully compatible
and execute such programs correctly as well, or, conversely,
implementations of the first and third types could be given additional
circuitry to look for, and produce error indications in the case of,
errors in the indication of parallelism.

Given that a program with an indication of parallelism would be
faster on one class of implementation, and not significantly
slower on the other classes of implementation, what is the utility
of this type of ISA?

Primarily, it is presumed that in many cases, programs written for the
ISA will be targeted at only one of the three classes of implementation
given above. Having a common ISA spanning these three classes allows
programs to run on CPUs of all three types, which is a benefit, but it
is also a benefit if a program primarily intended, for example, to be
used on the large implementations only, could be written in assembly
language, or generated by a compiler, in a simpler fashion without
making use of indication of parallelism or other VLIW features.

John Savard

On Sun, 11 Feb 2024 11:11:19 +0000, Quadibloc wrote:

> The invention?
>
> Here's a description worded in mild patentese...

And since even mild patentese is sufficient to make
people's eyes glaze over, here is a description
of the invention in plain English:

A class of ISA format where instructions are
organized into blocks, and where the first instruction
in a block can instead be a header including bits that
indicate when instructions can execute in parallel.

This lets programs include these headers, if they're
intended to run with maximum efficiency on the intermediate
implementations that use them, or be written more simply
without them if they're intended either for small
implementations that can't execute more than one
instruction at a time or large implementations that
take care of this sort of stuff automatically with
out-of-order execution.

John Savard

BGB wrote:

> On 2/10/2024 2:00 PM, MitchAlsup1 wrote:
>> Quadibloc wrote:
>>
>>> On Sat, 10 Feb 2024 18:46:32 +0000, MitchAlsup1 wrote:
>>>> Quadibloc wrote:
>>
>>>>> So I don't have a pile of earlier versions around to look at and
>>>>> discuss.
>>>>
>>>> You should if you ever want to patent any of the ideas.
>>
>>> That, too, is a very good point. However, Concertina II doesn't
>>> really embody anything in the way of original ideas. It's a very
>>> conventional architecture, only using techniques that have been
>>> tried before.
>>
>> The very fact that you packed everything everybody ever did into
>> one ISA is novel and passes the "If it is so obvious, why did nobody
>> every do it before" test.
>>

> Now, as for whether it makes sense to pack everything everyone ever did
> into a single ISA actually makes sense... Yeah, about that...

A patent does not have to be useful, just novel;...

Quadibloc <quadibloc@servername.invalid> schrieb:

> I live in Canada; in the United States, an invention can be patented
> within a year of its first disclosure,

That is just plain weird.

> but most countries have a
> stricter standard than that.

Most certainly.

On Sun, 11 Feb 2024 17:01:26 +0000, MitchAlsup1 wrote:

> A patent does not have to be useful, just novel;...

That is true in a legal sense, however in a practical
sense, since it costs money to file a patent, it's
only a patent that has some utility that gives you a
hope that your investment might lead to those sweet
licensing royalties flowing in.

John Savard

On Mon, 12 Feb 2024 19:22:42 +0000, Quadibloc wrote:

> On Sun, 11 Feb 2024 17:01:26 +0000, MitchAlsup1 wrote:
>
>> A patent does not have to be useful, just novel;...
>
> That is true in a legal sense, however in a practical
> sense, since it costs money to file a patent, it's
> only a patent that has some utility that gives you a
> hope that your investment might lead to those sweet
> licensing royalties flowing in.

This discussion about patents has inspired me to freely
disclose to the world, foregoing all hopes of remuneration,
an invention I came up with some time ago.

It's disclosed now on the bottom of this page:
http://www.quadibloc.com/comp/lineint.htm

Inspired by the IBM 1443 line printer, which prints
using hammers on horizontally moving physical letter
shapes, like a chain printer or train printer... but
where the letters are on a *rigid bar*...

I came up with the idea of replacing the rigid bar by
what looks for all the world like an ordinary print
_drum_, until you look at the letters on it. Instead
of looking like

AAAAA
BBBBB
CCCCC
.....

each row contains a repeated complete character set
for one print style. The drum shuttles back and forth
behind the hammers for printing - it only rotates one
position at a time to switch print styles or character
sets.

A printer like that, if one groups the most common
characters in a limited number of rows, could even print
in Chinese. A line printer with hammers, long before
laser printers were even invented!

To make money off of patenting that, I would also have to
invent a time machine...

John Savard

According to Quadibloc <quadibloc@servername.invalid>:
>On Sun, 11 Feb 2024 17:01:26 +0000, MitchAlsup1 wrote:
>
>> A patent does not have to be useful, just novel;...
>
>That is true in a legal sense, ...

Maybe. The invention disclosed in a patent has to work.

That's why the USPTO waives their right to get a model for everything
except perpetual motion machines.

--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly

Quadibloc wrote:

> On Mon, 12 Feb 2024 19:22:42 +0000, Quadibloc wrote:

>> On Sun, 11 Feb 2024 17:01:26 +0000, MitchAlsup1 wrote:
>>
>>> A patent does not have to be useful, just novel;...
>>
>> That is true in a legal sense, however in a practical
>> sense, since it costs money to file a patent, it's
>> only a patent that has some utility that gives you a
>> hope that your investment might lead to those sweet
>> licensing royalties flowing in.

> This discussion about patents has inspired me to freely
> disclose to the world, foregoing all hopes of remuneration,
> an invention I came up with some time ago.

> It's disclosed now on the bottom of this page:
> http://www.quadibloc.com/comp/lineint.htm

> Inspired by the IBM 1443 line printer, which prints
> using hammers on horizontally moving physical letter
> shapes, like a chain printer or train printer... but
> where the letters are on a *rigid bar*...

> I came up with the idea of replacing the rigid bar by
> what looks for all the world like an ordinary print
> _drum_, until you look at the letters on it. Instead
> of looking like

> AAAAA
> BBBBB
> CCCCC
> .....

We used to make a set of comment cards up that caused all of the hammers
to "fly" at the same time. That way we could take a quick nap, and when we
heard our; sound we would wake up, walk to the line printer and pick up our
printout. Bang-bang-bang-bang :: must have been hard on the line printer
mechanicals...

The 360/67 and the 1108 required different comment cards.....

> each row contains a repeated complete character set
> for one print style. The drum shuttles back and forth
> behind the hammers for printing - it only rotates one
> position at a time to switch print styles or character
> sets.

> A printer like that, if one groups the most common
> characters in a limited number of rows, could even print
> in Chinese. A line printer with hammers, long before
> laser printers were even invented!

> To make money off of patenting that, I would also have to
> invent a time machine...

> John Savard

On Wed, 14 Feb 2024 22:34:52 +0000, MitchAlsup1 wrote:

> We used to make a set of comment cards up that caused all of the hammers
> to "fly" at the same time. That way we could take a quick nap, and when we
> heard our; sound we would wake up, walk to the line printer and pick up our
> printout. Bang-bang-bang-bang :: must have been hard on the line printer
> mechanicals...

What it was _really_ hard on was the electonics that supplied
current to drive all those electromagnets on the same time.

On some printers, pulling that trick would blow fuses.

John Savard

According to Quadibloc <quadibloc@servername.invalid>:
>> We used to make a set of comment cards up that caused all of the hammers
>> to "fly" at the same time. That way we could take a quick nap, and when we
>> heard our; sound we would wake up, walk to the line printer and pick up our
>> printout. Bang-bang-bang-bang :: must have been hard on the line printer
>> mechanicals...
>
>What it was _really_ hard on was the electonics that supplied
>current to drive all those electromagnets on the same time.
>
>On some printers, pulling that trick would blow fuses.

Don't try that on an IBM 1403 N1 train printer. And don't ask me how I know.

--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly