*This is true on the basis of the meaning of its words*

The ultimate measure [of a correct simulation] is the correct x86
emulation of the x86 instructions in the order that they are specified.

The alternative is incorrectly emulating the x86 instructions in some
other order than they are specified.

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/24 05:35, olcott wrote:
> *This is true on the basis of the meaning of its words*
>
> The ultimate measure [of a correct simulation] is the correct x86
> emulation of the x86 instructions in the order that they are specified.
>
> The alternative is incorrectly emulating the x86 instructions in some
> other order than they are specified.
>

If an instruction specifies to call a function and the simulation does
something other than simulating the calling of the function, is it correct?

On 1/17/24 11:35 PM, olcott wrote:
> *This is true on the basis of the meaning of its words*
>
> The ultimate measure [of a correct simulation] is the correct x86
> emulation of the x86 instructions in the order that they are specified.

And continuing until it finishes. (since the question is DOES it finish).

>
> The alternative is incorrectly emulating the x86 instructions in some
> other order than they are specified.
>

No, you are neglecting that partial simulation is incorrect.

Also, "guessing" what a function call does without actually knowing is
incorrect.

You can't tell how long a road is until you follow the road all the way
to the end.

You are just showing how stupid you are.

This error has been pointed out to your multiple times, but apparently
you are so learning disabled that you can not understand it, or just so
set on your lies that you are just ignoring the actual facts.

On 1/18/2024 12:53 AM, Mikko wrote:
> On 2024-01-18 06:38:10 +0000, immibis said:
>
>> On 1/18/24 05:35, olcott wrote:
>>> *This is true on the basis of the meaning of its words*
>>>
>>> The ultimate measure [of a correct simulation] is the correct x86
>>> emulation of the x86 instructions in the order that they are specified.
>>>
>>> The alternative is incorrectly emulating the x86 instructions in some
>>> other order than they are specified.
>>>
>>
>> If an instruction specifies to call a function and the simulation does
>> something other than simulating the calling of the function, is it
>> correct?
>
> I would accept as correct if it simulates the effects of the call ( the
> return value and side effects) and continues the simulation at the
> instruction were the call would return.
>

When DD is correctly simulated by HH and D calls HH(DD,DD)
this call cannot possibly return.

main() invokes HH(DD,DD)
that simulates DD(DD)
that calls a simulated HH(DD,DD)
that simulates DD(DD)
that cannot possibly return to its caller.

01 int DD(ptr x) // ptr is pointer to int function
02 {
03 int Halt_Status = HH(x, x);
04 if (Halt_Status)
05 HERE: goto HERE;
06 return Halt_Status;
07 }
08
09 void main()
10 {
11 HH(DD,DD);
12 }

*Execution Trace*
Line 11: main() invokes HH(DD,DD);

*keeps repeating* (unless aborted)
Line 03: simulated DD(DD) invokes simulated HH(DD,DD) that simulates DD(DD)

*Simulation invariant*
DD correctly simulated by HH cannot possibly reach past its own line 03.

> If I had to construct a fake halt decider I would do an incorrect
> simulation where the simulated call H(D,D) returns the wrong value.
>
> Mikko
>

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/2024 12:38 AM, immibis wrote:
> On 1/18/24 05:35, olcott wrote:
>> *This is true on the basis of the meaning of its words*
>>
>> The ultimate measure [of a correct simulation] is the correct x86
>> emulation of the x86 instructions in the order that they are specified.
>>
>> The alternative is incorrectly emulating the x86 instructions in some
>> other order than they are specified.
>>
>
> If an instruction specifies to call a function and the simulation does
> something other than simulating the calling of the function, is it correct?

(a) If simulating termination analyzer H correctly determines that D
correctly simulated by H cannot possibly reach its own final state and
terminate normally then

(b) H can abort its simulation of D and correctly report that D
specifies a non-halting sequence of configurations.

HH(DD,DD) simulates itself simulating DD until it see that
D repeated the exact same states, thus is a correct simulation
up to the point where HH correctly determines that DD correctly
simulated by HH cannot possibly reach its own simulated final state.

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/2024 6:24 AM, Richard Damon wrote:
> On 1/17/24 11:35 PM, olcott wrote:
>> *This is true on the basis of the meaning of its words*
>>
>> The ultimate measure [of a correct simulation] is the correct x86
>> emulation of the x86 instructions in the order that they are specified.
>
> And continuing until it finishes. (since the question is DOES it finish).

(a) If simulating termination analyzer H correctly determines that D
correctly simulated by H cannot possibly reach its own simulated final
state and terminate normally then

(b) H can abort its simulation of D and correctly report that D
specifies a non-halting sequence of configurations.

>
>>
>> The alternative is incorrectly emulating the x86 instructions in some
>> other order than they are specified.
>>
>
> No, you are neglecting that partial simulation is incorrect.

Mike Terry has corrected you on this many times yet your ADD requires
the same thing to be repeated hundreds of times be3fore you ever notice
that it was said once.
>
> Also, "guessing" what a function call does without actually knowing is
> incorrect.
>

That you do not know the x86 language to verify that DD correctly
simulated by HH does derive a repeated state is not any rebuttal
what-so-ever.

Why do you insist that your own ignorance is a correct basis for a rebuttal?

Begin Local Halt Decider Simulation Execution Trace Stored at:113027
[00001c42][00113013][00113017] 55 push ebp
[00001c43][00113013][00113017] 8bec mov ebp,esp
[00001c45][0011300f][00102fe3] 51 push ecx
[00001c46][0011300f][00102fe3] 8b4508 mov eax,[ebp+08] ; DD
[00001c49][0011300b][00001c42] 50 push eax ; DD
[00001c4a][0011300b][00001c42] 8b4d08 mov ecx,[ebp+08] ; DD
[00001c4d][00113007][00001c42] 51 push ecx ; DD
[00001c4e][00113003][00001c53] e80ff7ffff call 00001362 ; HH
New slave_stack at:14da47
[00001c42][0015da3b][0015da3f] 55 push ebp
[00001c43][0015da3b][0015da3f] 8bec mov ebp,esp
[00001c45][0015da37][0014da0b] 51 push ecx
[00001c46][0015da37][0014da0b] 8b4508 mov eax,[ebp+08] ; DD
[00001c49][0015da33][00001c42] 50 push eax ; DD
[00001c4a][0015da33][00001c42] 8b4d08 mov ecx,[ebp+08] ; DD
[00001c4d][0015da2f][00001c42] 51 push ecx ; DD
[00001c4e][0015da2b][00001c53] e80ff7ffff call 00001362 ; HH

_DD()
[00001c42] 55 push ebp
[00001c43] 8bec mov ebp,esp
[00001c45] 51 push ecx
[00001c46] 8b4508 mov eax,[ebp+08] ; DD
[00001c49] 50 push eax ; DD
[00001c4a] 8b4d08 mov ecx,[ebp+08] ; DD
[00001c4d] 51 push ecx ; DD
[00001c4e] e80ff7ffff call 00001362 ; HH

*As proven above*
DD correctly simulated by HH cannot possibly
reach past the above machine address.

The ultimate measure [of a correct simulation] is the correct x86
emulation of the x86 instructions in the order that they are specified.

The alternative is incorrectly emulating the x86 instructions in some
other order than they are specified.

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/24 15:32, olcott wrote:
> On 1/18/2024 12:38 AM, immibis wrote:
>> On 1/18/24 05:35, olcott wrote:
>>> *This is true on the basis of the meaning of its words*
>>>
>>> The ultimate measure [of a correct simulation] is the correct x86
>>> emulation of the x86 instructions in the order that they are specified.
>>>
>>> The alternative is incorrectly emulating the x86 instructions in some
>>> other order than they are specified.
>>>
>>
>> If an instruction specifies to call a function and the simulation does
>> something other than simulating the calling of the function, is it
>> correct?
>
> (a) If simulating termination analyzer H correctly determines that D
> correctly simulated by H cannot possibly reach its own final state and
> terminate normally then

Polly want a cracker?

This is another way of saying: If D doesn't halt and H can prove it then.

>
> (b) H can abort its simulation of D and correctly report that D
> specifies a non-halting sequence of configurations.
>
> HH(DD,DD) simulates itself simulating DD until it see that
> D repeated the exact same states, thus is a correct simulation
> up to the point where HH correctly determines that DD correctly
> simulated by HH cannot possibly reach its own simulated final state.
>

If an instruction specifies to call a function and the simulation does
something other than simulating the calling of the function, is it correct?

On 1/18/24 15:47, olcott wrote:
> On 1/18/2024 6:24 AM, Richard Damon wrote:
>> On 1/17/24 11:35 PM, olcott wrote:
>>> *This is true on the basis of the meaning of its words*
>>>
>>> The ultimate measure [of a correct simulation] is the correct x86
>>> emulation of the x86 instructions in the order that they are specified.
>>
>> And continuing until it finishes. (since the question is DOES it finish).
>
> (a) If simulating termination analyzer H correctly determines that D
> correctly simulated by H cannot possibly reach its own simulated final
> state and terminate normally then
>
> (b) H can abort its simulation of D and correctly report that D
> specifies a non-halting sequence of configurations.
>
>>
>>>
>>> The alternative is incorrectly emulating the x86 instructions in some
>>> other order than they are specified.
>>>
>>
>> No, you are neglecting that partial simulation is incorrect.
>
> Mike Terry has corrected you on this many times yet your ADD requires
> the same thing to be repeated hundreds of times be3fore you ever notice
> that it was said once.
>>
>> Also, "guessing" what a function call does without actually knowing is
>> incorrect.
>>
>
> That you do not know the x86 language to verify that DD correctly
> simulated by HH does derive a repeated state is not any rebuttal
> what-so-ever.
>
> Why do you insist that your own ignorance is a correct basis for a
> rebuttal?
> > [computer generated garbage]

1. A Turing machine is a finite list of alphabet symbols, a default
symbol, a list of state numbers, an initial state number, a finite list
of accepting state numbers, and a transition table which maps each
(state × symbol) to another (state × symbol × direction).

2. The initial line of the execution trace trace(0) contains the initial
state number, and a tape consisting of one copy of the default symbol,
which is marked as the current position.

3. Each subsequent line of the execution trace trace(n+1) is formed
according to trace(n) by the following rules (applied simultaneously):
a. The active transition is the one which (trace(n) state number,
trace(n) tape symbol at trace(n) current position) maps to in the
transition table
b. trace(n+1) state number is the active transition's state
c. trace(n+1) symbol at trace(n) current position is the active
transition's symbol
d. trace(n+1) current position is trace(n) current position, moved
one cell left or right according to the active transition's direction
e. If the current position moves off the end of the tape, a default
symbol is added underneath the new current position.

4. The execution trace of a Turing machine is the sequence of steps
formed by repeatedly applying the rules in step 3 until it generates a
line with an accepting state number.

5. The execution trace of a Turing machine contains a finite number of
lines or an infinite number of lines.

6. If I tell you a Turing machine, can you figure out whether its
execution trace has a finite number of lines or an infinite number of lines?

Why do you insist that your own ignorance is a correct basis for a rebuttal?

On 18/01/2024 14:47, olcott wrote:
> On 1/18/2024 6:24 AM, Richard Damon wrote:
>> On 1/17/24 11:35 PM, olcott wrote:
>>> *This is true on the basis of the meaning of its words*
>>>
>>> The ultimate measure [of a correct simulation] is the correct x86
>>> emulation of the x86 instructions in the order that they are specified.
>>
>> And continuing until it finishes. (since the question is DOES it finish).
>
> (a) If simulating termination analyzer H correctly determines that D
> correctly simulated by H cannot possibly reach its own simulated final
> state and terminate normally then
>
> (b) H can abort its simulation of D and correctly report that D specifies a non-halting sequence of
> configurations.
>
>>
>>>
>>> The alternative is incorrectly emulating the x86 instructions in some
>>> other order than they are specified.
>>>
>>
>> No, you are neglecting that partial simulation is incorrect.
>
> Mike Terry has corrected you on this many times yet your ADD requires
> the same thing to be repeated hundreds of times be3fore you ever notice
> that it was said once.

I have not "corrected" anyone on this. Stop misrepresenting my position - that's a form of lying,
and I would have thought your religious views would dissuade you from behaving like that, even
inadvertently. (You must recognise by now that you often misunderstand the points people are making
- so even if /you/ think they are saying one thing, best to avoid telling everyone else what you
/think/ their position is - just say your own ideas in your own words, and you will avoid getting it
wrong.

Additionally, even if I had "corrected" Richard many times, SO WHAT? If you and Richard have some
disagreement over the exact meaning of a phrase, discuss and clarify the situation with Richard - no
need to drag 3rd parties into the matter in some kind of appeal to "authority".

Mike.

On 1/18/2024 10:37 AM, Mike Terry wrote:
> On 18/01/2024 14:47, olcott wrote:
>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>> On 1/17/24 11:35 PM, olcott wrote:
>>>> *This is true on the basis of the meaning of its words*
>>>>
>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>> emulation of the x86 instructions in the order that they are specified.
>>>
>>> And continuing until it finishes. (since the question is DOES it
>>> finish).
>>
>> (a) If simulating termination analyzer H correctly determines that D
>> correctly simulated by H cannot possibly reach its own simulated final
>> state and terminate normally then
>>
>> (b) H can abort its simulation of D and correctly report that D
>> specifies a non-halting sequence of configurations.
>>
>>>
>>>>
>>>> The alternative is incorrectly emulating the x86 instructions in some
>>>> other order than they are specified.
>>>>
>>>
>>> No, you are neglecting that partial simulation is incorrect.
>>
>> Mike Terry has corrected you on this many times yet your ADD requires
>> the same thing to be repeated hundreds of times be3fore you ever notice
>> that it was said once.
>
> I have not "corrected" anyone on this.  Stop misrepresenting my position
> - that's a form of lying, and I would have thought your religious views
> would dissuade you from behaving like that, even inadvertently.  (You
> must recognise by now that you often misunderstand the points people are
> making - so even if /you/ think they are saying one thing, best to avoid
> telling everyone else what you /think/ their position is - just say your
> own ideas in your own words, and you will avoid getting it wrong.
>
> Additionally, even if I had "corrected" Richard many times, SO WHAT?  If
> you and Richard have some disagreement over the exact meaning of a
> phrase, discuss and clarify the situation with Richard - no need to drag
> 3rd parties into the matter in some kind of appeal to "authority".
>
>
> Mike.
>

It is not that case that when N steps of DD are correctly simulated
by HH that these N steps are incorrectly simulated on the basis that
N+1 could have been simulated.

*Although you understand this Richard does not understand this*

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/24 18:15, olcott wrote:
> On 1/18/2024 10:37 AM, Mike Terry wrote:
>> On 18/01/2024 14:47, olcott wrote:
>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>> *This is true on the basis of the meaning of its words*
>>>>>
>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>> emulation of the x86 instructions in the order that they are
>>>>> specified.
>>>>
>>>> And continuing until it finishes. (since the question is DOES it
>>>> finish).
>>>
>>> (a) If simulating termination analyzer H correctly determines that D
>>> correctly simulated by H cannot possibly reach its own simulated final
>>> state and terminate normally then
>>>
>>> (b) H can abort its simulation of D and correctly report that D
>>> specifies a non-halting sequence of configurations.
>>>
>>>>
>>>>>
>>>>> The alternative is incorrectly emulating the x86 instructions in some
>>>>> other order than they are specified.
>>>>>
>>>>
>>>> No, you are neglecting that partial simulation is incorrect.
>>>
>>> Mike Terry has corrected you on this many times yet your ADD requires
>>> the same thing to be repeated hundreds of times be3fore you ever notice
>>> that it was said once.
>>
>> I have not "corrected" anyone on this.  Stop misrepresenting my
>> position - that's a form of lying, and I would have thought your
>> religious views would dissuade you from behaving like that, even
>> inadvertently.  (You must recognise by now that you often
>> misunderstand the points people are making - so even if /you/ think
>> they are saying one thing, best to avoid telling everyone else what
>> you /think/ their position is - just say your own ideas in your own
>> words, and you will avoid getting it wrong.
>>
>> Additionally, even if I had "corrected" Richard many times, SO WHAT?
>> If you and Richard have some disagreement over the exact meaning of a
>> phrase, discuss and clarify the situation with Richard - no need to
>> drag 3rd parties into the matter in some kind of appeal to "authority".
>>
>>
>> Mike.
>>
>
> It is not that case that when N steps of DD are correctly simulated
> by HH that these N steps are incorrectly simulated on the basis that
> N+1 could have been simulated.
>
> *Although you understand this Richard does not understand this*
>
>
The first N steps are not incorrect. The non-halting pattern recognition
is incorrect.

On 18/01/2024 17:15, olcott wrote:
> On 1/18/2024 10:37 AM, Mike Terry wrote:
>> On 18/01/2024 14:47, olcott wrote:
>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>> *This is true on the basis of the meaning of its words*
>>>>>
>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>> emulation of the x86 instructions in the order that they are specified.
>>>>
>>>> And continuing until it finishes. (since the question is DOES it finish).
>>>
>>> (a) If simulating termination analyzer H correctly determines that D
>>> correctly simulated by H cannot possibly reach its own simulated final
>>> state and terminate normally then
>>>
>>> (b) H can abort its simulation of D and correctly report that D specifies a non-halting sequence
>>> of configurations.
>>>
>>>>
>>>>>
>>>>> The alternative is incorrectly emulating the x86 instructions in some
>>>>> other order than they are specified.
>>>>>
>>>>
>>>> No, you are neglecting that partial simulation is incorrect.
>>>
>>> Mike Terry has corrected you on this many times yet your ADD requires
>>> the same thing to be repeated hundreds of times be3fore you ever notice
>>> that it was said once.
>>
>> I have not "corrected" anyone on this.  Stop misrepresenting my position - that's a form of lying,
>> and I would have thought your religious views would dissuade you from behaving like that, even
>> inadvertently.  (You must recognise by now that you often misunderstand the points people are
>> making - so even if /you/ think they are saying one thing, best to avoid telling everyone else
>> what you /think/ their position is - just say your own ideas in your own words, and you will avoid
>> getting it wrong.
>>
>> Additionally, even if I had "corrected" Richard many times, SO WHAT?  If you and Richard have some
>> disagreement over the exact meaning of a phrase, discuss and clarify the situation with Richard -
>> no need to drag 3rd parties into the matter in some kind of appeal to "authority".
>>
>>
>> Mike.
>>
>
> It is not that case that when N steps of DD are correctly simulated
> by HH that these N steps are incorrectly simulated on the basis that
> N+1 could have been simulated.
>
> *Although you understand this Richard does not understand this*

It is not a question of "correct understanding". It's just that different people may have slightly
different interpretations for the scope of a phrase like "correct simulation".

Do you think that Richard thinks the step by step x86 instruction emulation part of your code is
faulty? Maybe he does, but I doubt that... (and if not we are not disagreeing). More likely he
takes "correct simulation" to mean what I'd call "correct full simulation" or something. Perhaps
you should sort out the facts you actually agree on, then you can move on.

Mike.

On 1/18/2024 11:55 AM, Mike Terry wrote:
> On 18/01/2024 17:15, olcott wrote:
>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>> On 18/01/2024 14:47, olcott wrote:
>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>
>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>> emulation of the x86 instructions in the order that they are
>>>>>> specified.
>>>>>
>>>>> And continuing until it finishes. (since the question is DOES it
>>>>> finish).
>>>>
>>>> (a) If simulating termination analyzer H correctly determines that D
>>>> correctly simulated by H cannot possibly reach its own simulated final
>>>> state and terminate normally then
>>>>
>>>> (b) H can abort its simulation of D and correctly report that D
>>>> specifies a non-halting sequence of configurations.
>>>>
>>>>>
>>>>>>
>>>>>> The alternative is incorrectly emulating the x86 instructions in some
>>>>>> other order than they are specified.
>>>>>>
>>>>>
>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>
>>>> Mike Terry has corrected you on this many times yet your ADD requires
>>>> the same thing to be repeated hundreds of times be3fore you ever notice
>>>> that it was said once.
>>>
>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>> position - that's a form of lying, and I would have thought your
>>> religious views would dissuade you from behaving like that, even
>>> inadvertently.  (You must recognise by now that you often
>>> misunderstand the points people are making - so even if /you/ think
>>> they are saying one thing, best to avoid telling everyone else what
>>> you /think/ their position is - just say your own ideas in your own
>>> words, and you will avoid getting it wrong.
>>>
>>> Additionally, even if I had "corrected" Richard many times, SO WHAT?
>>> If you and Richard have some disagreement over the exact meaning of a
>>> phrase, discuss and clarify the situation with Richard - no need to
>>> drag 3rd parties into the matter in some kind of appeal to "authority".
>>>
>>>
>>> Mike.
>>>
>>
>> It is not that case that when N steps of DD are correctly simulated
>> by HH that these N steps are incorrectly simulated on the basis that
>> N+1 could have been simulated.
>>
>> *Although you understand this Richard does not understand this*
>
> It is not a question of "correct understanding".  It's just that
> different people may have slightly different interpretations for the
> scope of a phrase like "correct simulation".
>
> Do you think that Richard thinks the step by step x86 instruction
> emulation part of your code is faulty?  Maybe he does, but I doubt
> that... (and if not we are not disagreeing).  More likely he takes
> "correct simulation" to mean what I'd call "correct full simulation" or
> something.  Perhaps you should sort out the facts you actually agree on,
> then you can move on.
>
>
> Mike.
>

Richard insists that a correct partial simulation is totally incorrect.
--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/2024 11:55 AM, Mike Terry wrote:
> On 18/01/2024 17:15, olcott wrote:
>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>> On 18/01/2024 14:47, olcott wrote:
>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>
>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>> emulation of the x86 instructions in the order that they are
>>>>>> specified.
>>>>>
>>>>> And continuing until it finishes. (since the question is DOES it
>>>>> finish).
>>>>
>>>> (a) If simulating termination analyzer H correctly determines that D
>>>> correctly simulated by H cannot possibly reach its own simulated final
>>>> state and terminate normally then
>>>>
>>>> (b) H can abort its simulation of D and correctly report that D
>>>> specifies a non-halting sequence of configurations.
>>>>
>>>>>
>>>>>>
>>>>>> The alternative is incorrectly emulating the x86 instructions in some
>>>>>> other order than they are specified.
>>>>>>
>>>>>
>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>
>>>> Mike Terry has corrected you on this many times yet your ADD requires
>>>> the same thing to be repeated hundreds of times be3fore you ever notice
>>>> that it was said once.
>>>
>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>> position - that's a form of lying, and I would have thought your
>>> religious views would dissuade you from behaving like that, even
>>> inadvertently.  (You must recognise by now that you often
>>> misunderstand the points people are making - so even if /you/ think
>>> they are saying one thing, best to avoid telling everyone else what
>>> you /think/ their position is - just say your own ideas in your own
>>> words, and you will avoid getting it wrong.
>>>
>>> Additionally, even if I had "corrected" Richard many times, SO WHAT?
>>> If you and Richard have some disagreement over the exact meaning of a
>>> phrase, discuss and clarify the situation with Richard - no need to
>>> drag 3rd parties into the matter in some kind of appeal to "authority".
>>>
>>>
>>> Mike.
>>>
>>
>> It is not that case that when N steps of DD are correctly simulated
>> by HH that these N steps are incorrectly simulated on the basis that
>> N+1 could have been simulated.
>>
>> *Although you understand this Richard does not understand this*
>
> It is not a question of "correct understanding".  It's just that
> different people may have slightly different interpretations for the
> scope of a phrase like "correct simulation".
>
> Do you think that Richard thinks the step by step x86 instruction
> emulation part of your code is faulty?  Maybe he does, but I doubt
> that... (and if not we are not disagreeing).  More likely he takes
> "correct simulation" to mean what I'd call "correct full simulation" or
> something.  Perhaps you should sort out the facts you actually agree on,
> then you can move on.
>
>
> Mike.
>

Richard insists that a correct partial simulation is totally incorrect.

You insist that either (a) or (b) are incorrect or
that a correct simulation of D by H must incorrectly
emulate the x86 instructions of D or emulate them in
some other order than they are specified.

(a) If simulating termination analyzer H correctly determines that D
correctly simulated by H cannot possibly reach its own simulated final
state and terminate normally then

(b) H can abort its simulation of D and correctly report that D
specifies a non-halting sequence of configurations.

The ultimate measure [of a correct simulation] is the correct x86
emulation of the x86 instructions in the order that they are specified.
The alternative is incorrectly emulating the x86 instructions in some
other order than they are specified.

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/2024 11:53 AM, immibis wrote:
> On 1/18/24 18:15, olcott wrote:
>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>> On 18/01/2024 14:47, olcott wrote:
>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>
>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>> emulation of the x86 instructions in the order that they are
>>>>>> specified.
>>>>>
>>>>> And continuing until it finishes. (since the question is DOES it
>>>>> finish).
>>>>
>>>> (a) If simulating termination analyzer H correctly determines that D
>>>> correctly simulated by H cannot possibly reach its own simulated final
>>>> state and terminate normally then
>>>>
>>>> (b) H can abort its simulation of D and correctly report that D
>>>> specifies a non-halting sequence of configurations.
>>>>
>>>>>
>>>>>>
>>>>>> The alternative is incorrectly emulating the x86 instructions in some
>>>>>> other order than they are specified.
>>>>>>
>>>>>
>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>
>>>> Mike Terry has corrected you on this many times yet your ADD requires
>>>> the same thing to be repeated hundreds of times be3fore you ever notice
>>>> that it was said once.
>>>
>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>> position - that's a form of lying, and I would have thought your
>>> religious views would dissuade you from behaving like that, even
>>> inadvertently.  (You must recognise by now that you often
>>> misunderstand the points people are making - so even if /you/ think
>>> they are saying one thing, best to avoid telling everyone else what
>>> you /think/ their position is - just say your own ideas in your own
>>> words, and you will avoid getting it wrong.
>>>
>>> Additionally, even if I had "corrected" Richard many times, SO WHAT?
>>> If you and Richard have some disagreement over the exact meaning of a
>>> phrase, discuss and clarify the situation with Richard - no need to
>>> drag 3rd parties into the matter in some kind of appeal to "authority".
>>>
>>>
>>> Mike.
>>>
>>
>> It is not that case that when N steps of DD are correctly simulated
>> by HH that these N steps are incorrectly simulated on the basis that
>> N+1 could have been simulated.
>>
>> *Although you understand this Richard does not understand this*
>>
>>
> The first N steps are not incorrect. The non-halting pattern recognition
> is incorrect.

I have proved that DD correctly simulated by H cannot possibly reach
its final state. That you don't understand the x86 language well enough
to understand this IS YOUR MISTAKE NOT MINE.

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/24 20:05, olcott wrote:
> On 1/18/2024 11:55 AM, Mike Terry wrote:
>> On 18/01/2024 17:15, olcott wrote:
>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>> On 18/01/2024 14:47, olcott wrote:
>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>
>>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>> specified.
>>>>>>
>>>>>> And continuing until it finishes. (since the question is DOES it
>>>>>> finish).
>>>>>
>>>>> (a) If simulating termination analyzer H correctly determines that D
>>>>> correctly simulated by H cannot possibly reach its own simulated final
>>>>> state and terminate normally then
>>>>>
>>>>> (b) H can abort its simulation of D and correctly report that D
>>>>> specifies a non-halting sequence of configurations.
>>>>>
>>>>>>
>>>>>>>
>>>>>>> The alternative is incorrectly emulating the x86 instructions in
>>>>>>> some
>>>>>>> other order than they are specified.
>>>>>>>
>>>>>>
>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>
>>>>> Mike Terry has corrected you on this many times yet your ADD requires
>>>>> the same thing to be repeated hundreds of times be3fore you ever
>>>>> notice
>>>>> that it was said once.
>>>>
>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>> position - that's a form of lying, and I would have thought your
>>>> religious views would dissuade you from behaving like that, even
>>>> inadvertently.  (You must recognise by now that you often
>>>> misunderstand the points people are making - so even if /you/ think
>>>> they are saying one thing, best to avoid telling everyone else what
>>>> you /think/ their position is - just say your own ideas in your own
>>>> words, and you will avoid getting it wrong.
>>>>
>>>> Additionally, even if I had "corrected" Richard many times, SO WHAT?
>>>> If you and Richard have some disagreement over the exact meaning of
>>>> a phrase, discuss and clarify the situation with Richard - no need
>>>> to drag 3rd parties into the matter in some kind of appeal to
>>>> "authority".
>>>>
>>>>
>>>> Mike.
>>>>
>>>
>>> It is not that case that when N steps of DD are correctly simulated
>>> by HH that these N steps are incorrectly simulated on the basis that
>>> N+1 could have been simulated.
>>>
>>> *Although you understand this Richard does not understand this*
>>
>> It is not a question of "correct understanding".  It's just that
>> different people may have slightly different interpretations for the
>> scope of a phrase like "correct simulation".
>>
>> Do you think that Richard thinks the step by step x86 instruction
>> emulation part of your code is faulty?  Maybe he does, but I doubt
>> that... (and if not we are not disagreeing).  More likely he takes
>> "correct simulation" to mean what I'd call "correct full simulation"
>> or something.  Perhaps you should sort out the facts you actually
>> agree on, then you can move on.
>>
>>
>> Mike.
>>
>
> Richard insists that a correct partial simulation is totally incorrect.
>
> You insist that either (a) or (b) are incorrect or
> that a correct simulation of D by H must incorrectly
> emulate the x86 instructions of D or emulate them in
> some other order than they are specified.

Your simulation skips over the non-halting pattern detection
instructions by aborting the simulation before they execute.

>
> (a) If simulating termination analyzer H correctly determines that D
> correctly simulated by H cannot possibly reach its own simulated final
> state and terminate normally then
>
> (b) H can abort its simulation of D and correctly report that D
> specifies a non-halting sequence of configurations.
>
> The ultimate measure [of a correct simulation] is the correct x86
> emulation of the x86 instructions in the order that they are specified.
> The alternative is incorrectly emulating the x86 instructions in some
> other order than they are specified.
>
>
>

On 1/18/2024 1:19 PM, immibis wrote:
> On 1/18/24 20:05, olcott wrote:
>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>> On 18/01/2024 17:15, olcott wrote:
>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>
>>>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>>> specified.
>>>>>>>
>>>>>>> And continuing until it finishes. (since the question is DOES it
>>>>>>> finish).
>>>>>>
>>>>>> (a) If simulating termination analyzer H correctly determines that D
>>>>>> correctly simulated by H cannot possibly reach its own simulated
>>>>>> final
>>>>>> state and terminate normally then
>>>>>>
>>>>>> (b) H can abort its simulation of D and correctly report that D
>>>>>> specifies a non-halting sequence of configurations.
>>>>>>
>>>>>>>
>>>>>>>>
>>>>>>>> The alternative is incorrectly emulating the x86 instructions in
>>>>>>>> some
>>>>>>>> other order than they are specified.
>>>>>>>>
>>>>>>>
>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>
>>>>>> Mike Terry has corrected you on this many times yet your ADD requires
>>>>>> the same thing to be repeated hundreds of times be3fore you ever
>>>>>> notice
>>>>>> that it was said once.
>>>>>
>>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>>> position - that's a form of lying, and I would have thought your
>>>>> religious views would dissuade you from behaving like that, even
>>>>> inadvertently.  (You must recognise by now that you often
>>>>> misunderstand the points people are making - so even if /you/ think
>>>>> they are saying one thing, best to avoid telling everyone else what
>>>>> you /think/ their position is - just say your own ideas in your own
>>>>> words, and you will avoid getting it wrong.
>>>>>
>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>> meaning of a phrase, discuss and clarify the situation with Richard
>>>>> - no need to drag 3rd parties into the matter in some kind of
>>>>> appeal to "authority".
>>>>>
>>>>>
>>>>> Mike.
>>>>>
>>>>
>>>> It is not that case that when N steps of DD are correctly simulated
>>>> by HH that these N steps are incorrectly simulated on the basis that
>>>> N+1 could have been simulated.
>>>>
>>>> *Although you understand this Richard does not understand this*
>>>
>>> It is not a question of "correct understanding".  It's just that
>>> different people may have slightly different interpretations for the
>>> scope of a phrase like "correct simulation".
>>>
>>> Do you think that Richard thinks the step by step x86 instruction
>>> emulation part of your code is faulty?  Maybe he does, but I doubt
>>> that... (and if not we are not disagreeing).  More likely he takes
>>> "correct simulation" to mean what I'd call "correct full simulation"
>>> or something.  Perhaps you should sort out the facts you actually
>>> agree on, then you can move on.
>>>
>>>
>>> Mike.
>>>
>>
>> Richard insists that a correct partial simulation is totally incorrect.
>>
>> You insist that either (a) or (b) are incorrect or
>> that a correct simulation of D by H must incorrectly
>> emulate the x86 instructions of D or emulate them in
>> some other order than they are specified.
>
> Your simulation skips over the non-halting pattern detection
> instructions by aborting the simulation before they execute.
>

*Not so much*

Begin Local Halt Decider Simulation Execution Trace Stored at:113027
[00001c42][00113013][00113017] 55 push ebp
[00001c43][00113013][00113017] 8bec mov ebp,esp
[00001c45][0011300f][00102fe3] 51 push ecx
[00001c46][0011300f][00102fe3] 8b4508 mov eax,[ebp+08] ; DD
[00001c49][0011300b][00001c42] 50 push eax ; DD
[00001c4a][0011300b][00001c42] 8b4d08 mov ecx,[ebp+08] ; DD
[00001c4d][00113007][00001c42] 51 push ecx ; DD
[00001c4e][00113003][00001c53] e80ff7ffff call 00001362 ; HH
New slave_stack at:14da47
[00001c42][0015da3b][0015da3f] 55 push ebp
[00001c43][0015da3b][0015da3f] 8bec mov ebp,esp
[00001c45][0015da37][0014da0b] 51 push ecx
[00001c46][0015da37][0014da0b] 8b4508 mov eax,[ebp+08] ; DD
[00001c49][0015da33][00001c42] 50 push eax ; DD
[00001c4a][0015da33][00001c42] 8b4d08 mov ecx,[ebp+08] ; DD
[00001c4d][0015da2f][00001c42] 51 push ecx ; DD
[00001c4e][0015da2b][00001c53] e80ff7ffff call 00001362 ; HH

_DD()
[00001c42] 55 push ebp
[00001c43] 8bec mov ebp,esp
[00001c45] 51 push ecx
[00001c46] 8b4508 mov eax,[ebp+08] ; DD
[00001c49] 50 push eax ; DD
[00001c4a] 8b4d08 mov ecx,[ebp+08] ; DD
[00001c4d] 51 push ecx ; DD
[00001c4e] e80ff7ffff call 00001362 ; HH
[00001c53] 83c408 add esp,+08
[00001c56] 8945fc mov [ebp-04],eax
[00001c59] 837dfc00 cmp dword [ebp-04],+00
[00001c5d] 7402 jz 00001c61
[00001c5f] ebfe jmp 00001c5f
[00001c61] 8b45fc mov eax,[ebp-04]
[00001c64] 8be5 mov esp,ebp
[00001c66] 5d pop ebp
[00001c67] c3 ret
Size in bytes:(0038) [00001c67]

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/24 20:30, olcott wrote:
> On 1/18/2024 1:19 PM, immibis wrote:
>> On 1/18/24 20:05, olcott wrote:
>>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>>> On 18/01/2024 17:15, olcott wrote:
>>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>>
>>>>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>>>> specified.
>>>>>>>>
>>>>>>>> And continuing until it finishes. (since the question is DOES it
>>>>>>>> finish).
>>>>>>>
>>>>>>> (a) If simulating termination analyzer H correctly determines that D
>>>>>>> correctly simulated by H cannot possibly reach its own simulated
>>>>>>> final
>>>>>>> state and terminate normally then
>>>>>>>
>>>>>>> (b) H can abort its simulation of D and correctly report that D
>>>>>>> specifies a non-halting sequence of configurations.
>>>>>>>
>>>>>>>>
>>>>>>>>>
>>>>>>>>> The alternative is incorrectly emulating the x86 instructions
>>>>>>>>> in some
>>>>>>>>> other order than they are specified.
>>>>>>>>>
>>>>>>>>
>>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>>
>>>>>>> Mike Terry has corrected you on this many times yet your ADD
>>>>>>> requires
>>>>>>> the same thing to be repeated hundreds of times be3fore you ever
>>>>>>> notice
>>>>>>> that it was said once.
>>>>>>
>>>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>>>> position - that's a form of lying, and I would have thought your
>>>>>> religious views would dissuade you from behaving like that, even
>>>>>> inadvertently.  (You must recognise by now that you often
>>>>>> misunderstand the points people are making - so even if /you/
>>>>>> think they are saying one thing, best to avoid telling everyone
>>>>>> else what you /think/ their position is - just say your own ideas
>>>>>> in your own words, and you will avoid getting it wrong.
>>>>>>
>>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>>> meaning of a phrase, discuss and clarify the situation with
>>>>>> Richard - no need to drag 3rd parties into the matter in some kind
>>>>>> of appeal to "authority".
>>>>>>
>>>>>>
>>>>>> Mike.
>>>>>>
>>>>>
>>>>> It is not that case that when N steps of DD are correctly simulated
>>>>> by HH that these N steps are incorrectly simulated on the basis that
>>>>> N+1 could have been simulated.
>>>>>
>>>>> *Although you understand this Richard does not understand this*
>>>>
>>>> It is not a question of "correct understanding".  It's just that
>>>> different people may have slightly different interpretations for the
>>>> scope of a phrase like "correct simulation".
>>>>
>>>> Do you think that Richard thinks the step by step x86 instruction
>>>> emulation part of your code is faulty?  Maybe he does, but I doubt
>>>> that... (and if not we are not disagreeing).  More likely he takes
>>>> "correct simulation" to mean what I'd call "correct full simulation"
>>>> or something.  Perhaps you should sort out the facts you actually
>>>> agree on, then you can move on.
>>>>
>>>>
>>>> Mike.
>>>>
>>>
>>> Richard insists that a correct partial simulation is totally incorrect.
>>>
>>> You insist that either (a) or (b) are incorrect or
>>> that a correct simulation of D by H must incorrectly
>>> emulate the x86 instructions of D or emulate them in
>>> some other order than they are specified.
>>
>> Your simulation skips over the non-halting pattern detection
>> instructions by aborting the simulation before they execute.
>>
>
> *Not so much*
>
> Begin Local Halt Decider Simulation        Execution Trace Stored at:113027
> [00001c42][00113013][00113017] 55          push ebp
> [00001c43][00113013][00113017] 8bec        mov ebp,esp
> [00001c45][0011300f][00102fe3] 51          push ecx
> [00001c46][0011300f][00102fe3] 8b4508      mov eax,[ebp+08] ; DD
> [00001c49][0011300b][00001c42] 50          push eax         ; DD
> [00001c4a][0011300b][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
> [00001c4d][00113007][00001c42] 51          push ecx         ; DD
> [00001c4e][00113003][00001c53] e80ff7ffff  call 00001362    ; HH
> New slave_stack at:14da47
> [00001c42][0015da3b][0015da3f] 55          push ebp
> [00001c43][0015da3b][0015da3f] 8bec        mov ebp,esp
> [00001c45][0015da37][0014da0b] 51          push ecx
> [00001c46][0015da37][0014da0b] 8b4508      mov eax,[ebp+08] ; DD
> [00001c49][0015da33][00001c42] 50          push eax         ; DD
> [00001c4a][0015da33][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
> [00001c4d][0015da2f][00001c42] 51          push ecx         ; DD
> [00001c4e][0015da2b][00001c53] e80ff7ffff  call 00001362    ; HH
>
> _DD()
> [00001c42] 55         push ebp
> [00001c43] 8bec       mov ebp,esp
> [00001c45] 51         push ecx
> [00001c46] 8b4508     mov eax,[ebp+08] ; DD
> [00001c49] 50         push eax         ; DD
> [00001c4a] 8b4d08     mov ecx,[ebp+08] ; DD
> [00001c4d] 51         push ecx         ; DD
> [00001c4e] e80ff7ffff call 00001362    ; HH
> [00001c53] 83c408     add esp,+08
> [00001c56] 8945fc     mov [ebp-04],eax
> [00001c59] 837dfc00   cmp dword [ebp-04],+00
> [00001c5d] 7402       jz 00001c61
> [00001c5f] ebfe       jmp 00001c5f
> [00001c61] 8b45fc     mov eax,[ebp-04]
> [00001c64] 8be5       mov esp,ebp
> [00001c66] 5d         pop ebp
> [00001c67] c3         ret
> Size in bytes:(0038) [00001c67]
>

Where is the non-halting pattern detection being simulated?

On 1/18/2024 1:46 PM, immibis wrote:
> On 1/18/24 20:30, olcott wrote:
>> On 1/18/2024 1:19 PM, immibis wrote:
>>> On 1/18/24 20:05, olcott wrote:
>>>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>>>> On 18/01/2024 17:15, olcott wrote:
>>>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>>>
>>>>>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>>>>> specified.
>>>>>>>>>
>>>>>>>>> And continuing until it finishes. (since the question is DOES
>>>>>>>>> it finish).
>>>>>>>>
>>>>>>>> (a) If simulating termination analyzer H correctly determines
>>>>>>>> that D
>>>>>>>> correctly simulated by H cannot possibly reach its own simulated
>>>>>>>> final
>>>>>>>> state and terminate normally then
>>>>>>>>
>>>>>>>> (b) H can abort its simulation of D and correctly report that D
>>>>>>>> specifies a non-halting sequence of configurations.
>>>>>>>>
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> The alternative is incorrectly emulating the x86 instructions
>>>>>>>>>> in some
>>>>>>>>>> other order than they are specified.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>>>
>>>>>>>> Mike Terry has corrected you on this many times yet your ADD
>>>>>>>> requires
>>>>>>>> the same thing to be repeated hundreds of times be3fore you ever
>>>>>>>> notice
>>>>>>>> that it was said once.
>>>>>>>
>>>>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>>>>> position - that's a form of lying, and I would have thought your
>>>>>>> religious views would dissuade you from behaving like that, even
>>>>>>> inadvertently.  (You must recognise by now that you often
>>>>>>> misunderstand the points people are making - so even if /you/
>>>>>>> think they are saying one thing, best to avoid telling everyone
>>>>>>> else what you /think/ their position is - just say your own ideas
>>>>>>> in your own words, and you will avoid getting it wrong.
>>>>>>>
>>>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>>>> meaning of a phrase, discuss and clarify the situation with
>>>>>>> Richard - no need to drag 3rd parties into the matter in some
>>>>>>> kind of appeal to "authority".
>>>>>>>
>>>>>>>
>>>>>>> Mike.
>>>>>>>
>>>>>>
>>>>>> It is not that case that when N steps of DD are correctly simulated
>>>>>> by HH that these N steps are incorrectly simulated on the basis that
>>>>>> N+1 could have been simulated.
>>>>>>
>>>>>> *Although you understand this Richard does not understand this*
>>>>>
>>>>> It is not a question of "correct understanding".  It's just that
>>>>> different people may have slightly different interpretations for
>>>>> the scope of a phrase like "correct simulation".
>>>>>
>>>>> Do you think that Richard thinks the step by step x86 instruction
>>>>> emulation part of your code is faulty?  Maybe he does, but I doubt
>>>>> that... (and if not we are not disagreeing).  More likely he takes
>>>>> "correct simulation" to mean what I'd call "correct full
>>>>> simulation" or something.  Perhaps you should sort out the facts
>>>>> you actually agree on, then you can move on.
>>>>>
>>>>>
>>>>> Mike.
>>>>>
>>>>
>>>> Richard insists that a correct partial simulation is totally incorrect.
>>>>
>>>> You insist that either (a) or (b) are incorrect or
>>>> that a correct simulation of D by H must incorrectly
>>>> emulate the x86 instructions of D or emulate them in
>>>> some other order than they are specified.
>>>
>>> Your simulation skips over the non-halting pattern detection
>>> instructions by aborting the simulation before they execute.
>>>
>>
>> *Not so much*
>>
>> Begin Local Halt Decider Simulation        Execution Trace Stored
>> at:113027
>> [00001c42][00113013][00113017] 55          push ebp
>> [00001c43][00113013][00113017] 8bec        mov ebp,esp
>> [00001c45][0011300f][00102fe3] 51          push ecx
>> [00001c46][0011300f][00102fe3] 8b4508      mov eax,[ebp+08] ; DD
>> [00001c49][0011300b][00001c42] 50          push eax         ; DD
>> [00001c4a][0011300b][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>> [00001c4d][00113007][00001c42] 51          push ecx         ; DD
>> [00001c4e][00113003][00001c53] e80ff7ffff  call 00001362    ; HH
>> New slave_stack at:14da47
>> [00001c42][0015da3b][0015da3f] 55          push ebp
>> [00001c43][0015da3b][0015da3f] 8bec        mov ebp,esp
>> [00001c45][0015da37][0014da0b] 51          push ecx
>> [00001c46][0015da37][0014da0b] 8b4508      mov eax,[ebp+08] ; DD
>> [00001c49][0015da33][00001c42] 50          push eax         ; DD
>> [00001c4a][0015da33][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>> [00001c4d][0015da2f][00001c42] 51          push ecx         ; DD
>> [00001c4e][0015da2b][00001c53] e80ff7ffff  call 00001362    ; HH
>>
>> _DD()
>> [00001c42] 55         push ebp
>> [00001c43] 8bec       mov ebp,esp
>> [00001c45] 51         push ecx
>> [00001c46] 8b4508     mov eax,[ebp+08] ; DD
>> [00001c49] 50         push eax         ; DD
>> [00001c4a] 8b4d08     mov ecx,[ebp+08] ; DD
>> [00001c4d] 51         push ecx         ; DD
>> [00001c4e] e80ff7ffff call 00001362    ; HH
>> [00001c53] 83c408     add esp,+08
>> [00001c56] 8945fc     mov [ebp-04],eax
>> [00001c59] 837dfc00   cmp dword [ebp-04],+00
>> [00001c5d] 7402       jz 00001c61
>> [00001c5f] ebfe       jmp 00001c5f
>> [00001c61] 8b45fc     mov eax,[ebp-04]
>> [00001c64] 8be5       mov esp,ebp
>> [00001c66] 5d         pop ebp
>> [00001c67] c3         ret
>> Size in bytes:(0038) [00001c67]
>>
>
> Where is the non-halting pattern detection being simulated?

repeating instructions [00001c42] to [00001c4e]

--
Copyright 2023 Olcott "Talent hits a target no one else can hit; Genius
hits a target no one else can see." Arthur Schopenhauer

On 1/18/24 21:03, olcott wrote:
> On 1/18/2024 1:46 PM, immibis wrote:
>> On 1/18/24 20:30, olcott wrote:
>>> On 1/18/2024 1:19 PM, immibis wrote:
>>>> On 1/18/24 20:05, olcott wrote:
>>>>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>>>>> On 18/01/2024 17:15, olcott wrote:
>>>>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>>>>
>>>>>>>>>>> The ultimate measure [of a correct simulation] is the correct
>>>>>>>>>>> x86
>>>>>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>>>>>> specified.
>>>>>>>>>>
>>>>>>>>>> And continuing until it finishes. (since the question is DOES
>>>>>>>>>> it finish).
>>>>>>>>>
>>>>>>>>> (a) If simulating termination analyzer H correctly determines
>>>>>>>>> that D
>>>>>>>>> correctly simulated by H cannot possibly reach its own
>>>>>>>>> simulated final
>>>>>>>>> state and terminate normally then
>>>>>>>>>
>>>>>>>>> (b) H can abort its simulation of D and correctly report that D
>>>>>>>>> specifies a non-halting sequence of configurations.
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> The alternative is incorrectly emulating the x86 instructions
>>>>>>>>>>> in some
>>>>>>>>>>> other order than they are specified.
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>>>>
>>>>>>>>> Mike Terry has corrected you on this many times yet your ADD
>>>>>>>>> requires
>>>>>>>>> the same thing to be repeated hundreds of times be3fore you
>>>>>>>>> ever notice
>>>>>>>>> that it was said once.
>>>>>>>>
>>>>>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>>>>>> position - that's a form of lying, and I would have thought your
>>>>>>>> religious views would dissuade you from behaving like that, even
>>>>>>>> inadvertently.  (You must recognise by now that you often
>>>>>>>> misunderstand the points people are making - so even if /you/
>>>>>>>> think they are saying one thing, best to avoid telling everyone
>>>>>>>> else what you /think/ their position is - just say your own
>>>>>>>> ideas in your own words, and you will avoid getting it wrong.
>>>>>>>>
>>>>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>>>>> meaning of a phrase, discuss and clarify the situation with
>>>>>>>> Richard - no need to drag 3rd parties into the matter in some
>>>>>>>> kind of appeal to "authority".
>>>>>>>>
>>>>>>>>
>>>>>>>> Mike.
>>>>>>>>
>>>>>>>
>>>>>>> It is not that case that when N steps of DD are correctly simulated
>>>>>>> by HH that these N steps are incorrectly simulated on the basis that
>>>>>>> N+1 could have been simulated.
>>>>>>>
>>>>>>> *Although you understand this Richard does not understand this*
>>>>>>
>>>>>> It is not a question of "correct understanding".  It's just that
>>>>>> different people may have slightly different interpretations for
>>>>>> the scope of a phrase like "correct simulation".
>>>>>>
>>>>>> Do you think that Richard thinks the step by step x86 instruction
>>>>>> emulation part of your code is faulty?  Maybe he does, but I doubt
>>>>>> that... (and if not we are not disagreeing).  More likely he takes
>>>>>> "correct simulation" to mean what I'd call "correct full
>>>>>> simulation" or something.  Perhaps you should sort out the facts
>>>>>> you actually agree on, then you can move on.
>>>>>>
>>>>>>
>>>>>> Mike.
>>>>>>
>>>>>
>>>>> Richard insists that a correct partial simulation is totally
>>>>> incorrect.
>>>>>
>>>>> You insist that either (a) or (b) are incorrect or
>>>>> that a correct simulation of D by H must incorrectly
>>>>> emulate the x86 instructions of D or emulate them in
>>>>> some other order than they are specified.
>>>>
>>>> Your simulation skips over the non-halting pattern detection
>>>> instructions by aborting the simulation before they execute.
>>>>
>>>
>>> *Not so much*
>>>
>>> Begin Local Halt Decider Simulation        Execution Trace Stored
>>> at:113027
>>> [00001c42][00113013][00113017] 55          push ebp
>>> [00001c43][00113013][00113017] 8bec        mov ebp,esp
>>> [00001c45][0011300f][00102fe3] 51          push ecx
>>> [00001c46][0011300f][00102fe3] 8b4508      mov eax,[ebp+08] ; DD
>>> [00001c49][0011300b][00001c42] 50          push eax         ; DD
>>> [00001c4a][0011300b][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>> [00001c4d][00113007][00001c42] 51          push ecx         ; DD
>>> [00001c4e][00113003][00001c53] e80ff7ffff  call 00001362    ; HH
>>> New slave_stack at:14da47
>>> [00001c42][0015da3b][0015da3f] 55          push ebp
>>> [00001c43][0015da3b][0015da3f] 8bec        mov ebp,esp
>>> [00001c45][0015da37][0014da0b] 51          push ecx
>>> [00001c46][0015da37][0014da0b] 8b4508      mov eax,[ebp+08] ; DD
>>> [00001c49][0015da33][00001c42] 50          push eax         ; DD
>>> [00001c4a][0015da33][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>> [00001c4d][0015da2f][00001c42] 51          push ecx         ; DD
>>> [00001c4e][0015da2b][00001c53] e80ff7ffff  call 00001362    ; HH
>>>
>>> _DD()
>>> [00001c42] 55         push ebp
>>> [00001c43] 8bec       mov ebp,esp
>>> [00001c45] 51         push ecx
>>> [00001c46] 8b4508     mov eax,[ebp+08] ; DD
>>> [00001c49] 50         push eax         ; DD
>>> [00001c4a] 8b4d08     mov ecx,[ebp+08] ; DD
>>> [00001c4d] 51         push ecx         ; DD
>>> [00001c4e] e80ff7ffff call 00001362    ; HH
>>> [00001c53] 83c408     add esp,+08
>>> [00001c56] 8945fc     mov [ebp-04],eax
>>> [00001c59] 837dfc00   cmp dword [ebp-04],+00
>>> [00001c5d] 7402       jz 00001c61
>>> [00001c5f] ebfe       jmp 00001c5f
>>> [00001c61] 8b45fc     mov eax,[ebp-04]
>>> [00001c64] 8be5       mov esp,ebp
>>> [00001c66] 5d         pop ebp
>>> [00001c67] c3         ret
>>> Size in bytes:(0038) [00001c67]
>>>
>>
>> Where is the non-halting pattern detection being simulated?
>
> repeating instructions [00001c42] to [00001c4e]
>
Which instruction detects non-halting patterns?

On 1/18/2024 2:42 PM, immibis wrote:
> On 1/18/24 21:03, olcott wrote:
>> On 1/18/2024 1:46 PM, immibis wrote:
>>> On 1/18/24 20:30, olcott wrote:
>>>> On 1/18/2024 1:19 PM, immibis wrote:
>>>>> On 1/18/24 20:05, olcott wrote:
>>>>>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>>>>>> On 18/01/2024 17:15, olcott wrote:
>>>>>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>>>>>
>>>>>>>>>>>> The ultimate measure [of a correct simulation] is the
>>>>>>>>>>>> correct x86
>>>>>>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>>>>>>> specified.
>>>>>>>>>>>
>>>>>>>>>>> And continuing until it finishes. (since the question is DOES
>>>>>>>>>>> it finish).
>>>>>>>>>>
>>>>>>>>>> (a) If simulating termination analyzer H correctly determines
>>>>>>>>>> that D
>>>>>>>>>> correctly simulated by H cannot possibly reach its own
>>>>>>>>>> simulated final
>>>>>>>>>> state and terminate normally then
>>>>>>>>>>
>>>>>>>>>> (b) H can abort its simulation of D and correctly report that
>>>>>>>>>> D specifies a non-halting sequence of configurations.
>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> The alternative is incorrectly emulating the x86
>>>>>>>>>>>> instructions in some
>>>>>>>>>>>> other order than they are specified.
>>>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>>>>>
>>>>>>>>>> Mike Terry has corrected you on this many times yet your ADD
>>>>>>>>>> requires
>>>>>>>>>> the same thing to be repeated hundreds of times be3fore you
>>>>>>>>>> ever notice
>>>>>>>>>> that it was said once.
>>>>>>>>>
>>>>>>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>>>>>>> position - that's a form of lying, and I would have thought
>>>>>>>>> your religious views would dissuade you from behaving like
>>>>>>>>> that, even inadvertently.  (You must recognise by now that you
>>>>>>>>> often misunderstand the points people are making - so even if
>>>>>>>>> /you/ think they are saying one thing, best to avoid telling
>>>>>>>>> everyone else what you /think/ their position is - just say
>>>>>>>>> your own ideas in your own words, and you will avoid getting it
>>>>>>>>> wrong.
>>>>>>>>>
>>>>>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>>>>>> meaning of a phrase, discuss and clarify the situation with
>>>>>>>>> Richard - no need to drag 3rd parties into the matter in some
>>>>>>>>> kind of appeal to "authority".
>>>>>>>>>
>>>>>>>>>
>>>>>>>>> Mike.
>>>>>>>>>
>>>>>>>>
>>>>>>>> It is not that case that when N steps of DD are correctly simulated
>>>>>>>> by HH that these N steps are incorrectly simulated on the basis
>>>>>>>> that
>>>>>>>> N+1 could have been simulated.
>>>>>>>>
>>>>>>>> *Although you understand this Richard does not understand this*
>>>>>>>
>>>>>>> It is not a question of "correct understanding".  It's just that
>>>>>>> different people may have slightly different interpretations for
>>>>>>> the scope of a phrase like "correct simulation".
>>>>>>>
>>>>>>> Do you think that Richard thinks the step by step x86 instruction
>>>>>>> emulation part of your code is faulty?  Maybe he does, but I
>>>>>>> doubt that... (and if not we are not disagreeing).  More likely
>>>>>>> he takes "correct simulation" to mean what I'd call "correct full
>>>>>>> simulation" or something.  Perhaps you should sort out the facts
>>>>>>> you actually agree on, then you can move on.
>>>>>>>
>>>>>>>
>>>>>>> Mike.
>>>>>>>
>>>>>>
>>>>>> Richard insists that a correct partial simulation is totally
>>>>>> incorrect.
>>>>>>
>>>>>> You insist that either (a) or (b) are incorrect or
>>>>>> that a correct simulation of D by H must incorrectly
>>>>>> emulate the x86 instructions of D or emulate them in
>>>>>> some other order than they are specified.
>>>>>
>>>>> Your simulation skips over the non-halting pattern detection
>>>>> instructions by aborting the simulation before they execute.
>>>>>
>>>>
>>>> *Not so much*
>>>>
>>>> Begin Local Halt Decider Simulation        Execution Trace Stored
>>>> at:113027
>>>> [00001c42][00113013][00113017] 55          push ebp
>>>> [00001c43][00113013][00113017] 8bec        mov ebp,esp
>>>> [00001c45][0011300f][00102fe3] 51          push ecx
>>>> [00001c46][0011300f][00102fe3] 8b4508      mov eax,[ebp+08] ; DD
>>>> [00001c49][0011300b][00001c42] 50          push eax         ; DD
>>>> [00001c4a][0011300b][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>>> [00001c4d][00113007][00001c42] 51          push ecx         ; DD
>>>> [00001c4e][00113003][00001c53] e80ff7ffff  call 00001362    ; HH
>>>> New slave_stack at:14da47
>>>> [00001c42][0015da3b][0015da3f] 55          push ebp
>>>> [00001c43][0015da3b][0015da3f] 8bec        mov ebp,esp
>>>> [00001c45][0015da37][0014da0b] 51          push ecx
>>>> [00001c46][0015da37][0014da0b] 8b4508      mov eax,[ebp+08] ; DD
>>>> [00001c49][0015da33][00001c42] 50          push eax         ; DD
>>>> [00001c4a][0015da33][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>>> [00001c4d][0015da2f][00001c42] 51          push ecx         ; DD
>>>> [00001c4e][0015da2b][00001c53] e80ff7ffff  call 00001362    ; HH
>>>>
>>>> _DD()
>>>> [00001c42] 55         push ebp
>>>> [00001c43] 8bec       mov ebp,esp
>>>> [00001c45] 51         push ecx
>>>> [00001c46] 8b4508     mov eax,[ebp+08] ; DD
>>>> [00001c49] 50         push eax         ; DD
>>>> [00001c4a] 8b4d08     mov ecx,[ebp+08] ; DD
>>>> [00001c4d] 51         push ecx         ; DD
>>>> [00001c4e] e80ff7ffff call 00001362    ; HH
>>>> [00001c53] 83c408     add esp,+08
>>>> [00001c56] 8945fc     mov [ebp-04],eax
>>>> [00001c59] 837dfc00   cmp dword [ebp-04],+00
>>>> [00001c5d] 7402       jz 00001c61
>>>> [00001c5f] ebfe       jmp 00001c5f
>>>> [00001c61] 8b45fc     mov eax,[ebp-04]
>>>> [00001c64] 8be5       mov esp,ebp
>>>> [00001c66] 5d         pop ebp
>>>> [00001c67] c3         ret
>>>> Size in bytes:(0038) [00001c67]
>>>>
>>>
>>> Where is the non-halting pattern detection being simulated?
>>
>> repeating instructions [00001c42] to [00001c4e]
>>
> Which instruction detects non-halting patterns?

On 1/18/24 9:32 AM, olcott wrote:
> On 1/18/2024 12:38 AM, immibis wrote:
>> On 1/18/24 05:35, olcott wrote:
>>> *This is true on the basis of the meaning of its words*
>>>
>>> The ultimate measure [of a correct simulation] is the correct x86
>>> emulation of the x86 instructions in the order that they are specified.
>>>
>>> The alternative is incorrectly emulating the x86 instructions in some
>>> other order than they are specified.
>>>
>>
>> If an instruction specifies to call a function and the simulation does
>> something other than simulating the calling of the function, is it
>> correct?
>
> (a) If simulating termination analyzer H correctly determines that D
> correctly simulated by H cannot possibly reach its own final state and
> terminate normally then

Which it doesn't do, since THIS H never correctly simulates its input to
the end.

>
> (b) H can abort its simulation of D and correctly report that D
> specifies a non-halting sequence of configurations.
>
> HH(DD,DD) simulates itself simulating DD until it see that
> D repeated the exact same states, thus is a correct simulation
> up to the point where HH correctly determines that DD correctly
> simulated by HH cannot possibly reach its own simulated final state.
>

But H and HH are different machines, so D and DD are different input.

Two things that are different are not the same.

On 1/18/24 9:18 AM, olcott wrote:
> On 1/18/2024 12:53 AM, Mikko wrote:
>> On 2024-01-18 06:38:10 +0000, immibis said:
>>
>>> On 1/18/24 05:35, olcott wrote:
>>>> *This is true on the basis of the meaning of its words*
>>>>
>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>> emulation of the x86 instructions in the order that they are specified.
>>>>
>>>> The alternative is incorrectly emulating the x86 instructions in some
>>>> other order than they are specified.
>>>>
>>>
>>> If an instruction specifies to call a function and the simulation
>>> does something other than simulating the calling of the function, is
>>> it correct?
>>
>> I would accept as correct if it simulates the effects of the call ( the
>> return value and side effects) and continues the simulation at the
>> instruction were the call would return.
>>
>
> When DD is correctly simulated by HH and D calls HH(DD,DD)
> this call cannot possibly return.

But D doesn't call HH(DD,DD), it calls H(D,D).

DD and D are different programs since HH and H are different programs.

>
> main() invokes HH(DD,DD)
> that simulates DD(DD)
> that calls a simulated HH(DD,DD)
> that simulates DD(DD)
> that cannot possibly return to its caller.
>
> 01 int DD(ptr x)  // ptr is pointer to int function
> 02 {
> 03   int Halt_Status = HH(x, x);
> 04   if (Halt_Status)
> 05     HERE: goto HERE;
> 06   return Halt_Status;
> 07 }
> 08
> 09 void main()
> 10 {
> 11   HH(DD,DD);
> 12 }
>
> *Execution Trace*
> Line 11: main() invokes HH(DD,DD);
>
> *keeps repeating* (unless aborted)
> Line 03: simulated DD(DD) invokes simulated HH(DD,DD) that simulates DD(DD)
>
> *Simulation invariant*
> DD correctly simulated by HH cannot possibly reach past its own line 03.
>
>
>> If I had to construct a fake halt decider I would do an incorrect
>> simulation where the simulated call H(D,D) returns the wrong value.
>>
>> Mikko
>>
>

On 1/18/24 3:03 PM, olcott wrote:
> On 1/18/2024 1:46 PM, immibis wrote:
>> On 1/18/24 20:30, olcott wrote:
>>> On 1/18/2024 1:19 PM, immibis wrote:
>>>> On 1/18/24 20:05, olcott wrote:
>>>>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>>>>> On 18/01/2024 17:15, olcott wrote:
>>>>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>>>>
>>>>>>>>>>> The ultimate measure [of a correct simulation] is the correct
>>>>>>>>>>> x86
>>>>>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>>>>>> specified.
>>>>>>>>>>
>>>>>>>>>> And continuing until it finishes. (since the question is DOES
>>>>>>>>>> it finish).
>>>>>>>>>
>>>>>>>>> (a) If simulating termination analyzer H correctly determines
>>>>>>>>> that D
>>>>>>>>> correctly simulated by H cannot possibly reach its own
>>>>>>>>> simulated final
>>>>>>>>> state and terminate normally then
>>>>>>>>>
>>>>>>>>> (b) H can abort its simulation of D and correctly report that D
>>>>>>>>> specifies a non-halting sequence of configurations.
>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>>>
>>>>>>>>>>> The alternative is incorrectly emulating the x86 instructions
>>>>>>>>>>> in some
>>>>>>>>>>> other order than they are specified.
>>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>>>>
>>>>>>>>> Mike Terry has corrected you on this many times yet your ADD
>>>>>>>>> requires
>>>>>>>>> the same thing to be repeated hundreds of times be3fore you
>>>>>>>>> ever notice
>>>>>>>>> that it was said once.
>>>>>>>>
>>>>>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>>>>>> position - that's a form of lying, and I would have thought your
>>>>>>>> religious views would dissuade you from behaving like that, even
>>>>>>>> inadvertently.  (You must recognise by now that you often
>>>>>>>> misunderstand the points people are making - so even if /you/
>>>>>>>> think they are saying one thing, best to avoid telling everyone
>>>>>>>> else what you /think/ their position is - just say your own
>>>>>>>> ideas in your own words, and you will avoid getting it wrong.
>>>>>>>>
>>>>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>>>>> meaning of a phrase, discuss and clarify the situation with
>>>>>>>> Richard - no need to drag 3rd parties into the matter in some
>>>>>>>> kind of appeal to "authority".
>>>>>>>>
>>>>>>>>
>>>>>>>> Mike.
>>>>>>>>
>>>>>>>
>>>>>>> It is not that case that when N steps of DD are correctly simulated
>>>>>>> by HH that these N steps are incorrectly simulated on the basis that
>>>>>>> N+1 could have been simulated.
>>>>>>>
>>>>>>> *Although you understand this Richard does not understand this*
>>>>>>
>>>>>> It is not a question of "correct understanding".  It's just that
>>>>>> different people may have slightly different interpretations for
>>>>>> the scope of a phrase like "correct simulation".
>>>>>>
>>>>>> Do you think that Richard thinks the step by step x86 instruction
>>>>>> emulation part of your code is faulty?  Maybe he does, but I doubt
>>>>>> that... (and if not we are not disagreeing).  More likely he takes
>>>>>> "correct simulation" to mean what I'd call "correct full
>>>>>> simulation" or something.  Perhaps you should sort out the facts
>>>>>> you actually agree on, then you can move on.
>>>>>>
>>>>>>
>>>>>> Mike.
>>>>>>
>>>>>
>>>>> Richard insists that a correct partial simulation is totally
>>>>> incorrect.
>>>>>
>>>>> You insist that either (a) or (b) are incorrect or
>>>>> that a correct simulation of D by H must incorrectly
>>>>> emulate the x86 instructions of D or emulate them in
>>>>> some other order than they are specified.
>>>>
>>>> Your simulation skips over the non-halting pattern detection
>>>> instructions by aborting the simulation before they execute.
>>>>
>>>
>>> *Not so much*
>>>
>>> Begin Local Halt Decider Simulation        Execution Trace Stored
>>> at:113027
>>> [00001c42][00113013][00113017] 55          push ebp
>>> [00001c43][00113013][00113017] 8bec        mov ebp,esp
>>> [00001c45][0011300f][00102fe3] 51          push ecx
>>> [00001c46][0011300f][00102fe3] 8b4508      mov eax,[ebp+08] ; DD
>>> [00001c49][0011300b][00001c42] 50          push eax         ; DD
>>> [00001c4a][0011300b][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>> [00001c4d][00113007][00001c42] 51          push ecx         ; DD
>>> [00001c4e][00113003][00001c53] e80ff7ffff  call 00001362    ; HH
>>> New slave_stack at:14da47
>>> [00001c42][0015da3b][0015da3f] 55          push ebp
>>> [00001c43][0015da3b][0015da3f] 8bec        mov ebp,esp
>>> [00001c45][0015da37][0014da0b] 51          push ecx
>>> [00001c46][0015da37][0014da0b] 8b4508      mov eax,[ebp+08] ; DD
>>> [00001c49][0015da33][00001c42] 50          push eax         ; DD
>>> [00001c4a][0015da33][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>> [00001c4d][0015da2f][00001c42] 51          push ecx         ; DD
>>> [00001c4e][0015da2b][00001c53] e80ff7ffff  call 00001362    ; HH
>>>
>>> _DD()
>>> [00001c42] 55         push ebp
>>> [00001c43] 8bec       mov ebp,esp
>>> [00001c45] 51         push ecx
>>> [00001c46] 8b4508     mov eax,[ebp+08] ; DD
>>> [00001c49] 50         push eax         ; DD
>>> [00001c4a] 8b4d08     mov ecx,[ebp+08] ; DD
>>> [00001c4d] 51         push ecx         ; DD
>>> [00001c4e] e80ff7ffff call 00001362    ; HH
>>> [00001c53] 83c408     add esp,+08
>>> [00001c56] 8945fc     mov [ebp-04],eax
>>> [00001c59] 837dfc00   cmp dword [ebp-04],+00
>>> [00001c5d] 7402       jz 00001c61
>>> [00001c5f] ebfe       jmp 00001c5f
>>> [00001c61] 8b45fc     mov eax,[ebp-04]
>>> [00001c64] 8be5       mov esp,ebp
>>> [00001c66] 5d         pop ebp
>>> [00001c67] c3         ret
>>> Size in bytes:(0038) [00001c67]
>>>
>>
>> Where is the non-halting pattern detection being simulated?
>
> repeating instructions [00001c42] to [00001c4e]
>

ignoring that the code at 00001362 will change this behavior if this
decider will ever answer.

Code not looked at means incorrect reasoning.

On 1/18/24 2:30 PM, olcott wrote:
> On 1/18/2024 1:19 PM, immibis wrote:
>> On 1/18/24 20:05, olcott wrote:
>>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>>> On 18/01/2024 17:15, olcott wrote:
>>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>>
>>>>>>>>> The ultimate measure [of a correct simulation] is the correct x86
>>>>>>>>> emulation of the x86 instructions in the order that they are
>>>>>>>>> specified.
>>>>>>>>
>>>>>>>> And continuing until it finishes. (since the question is DOES it
>>>>>>>> finish).
>>>>>>>
>>>>>>> (a) If simulating termination analyzer H correctly determines that D
>>>>>>> correctly simulated by H cannot possibly reach its own simulated
>>>>>>> final
>>>>>>> state and terminate normally then
>>>>>>>
>>>>>>> (b) H can abort its simulation of D and correctly report that D
>>>>>>> specifies a non-halting sequence of configurations.
>>>>>>>
>>>>>>>>
>>>>>>>>>
>>>>>>>>> The alternative is incorrectly emulating the x86 instructions
>>>>>>>>> in some
>>>>>>>>> other order than they are specified.
>>>>>>>>>
>>>>>>>>
>>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>>
>>>>>>> Mike Terry has corrected you on this many times yet your ADD
>>>>>>> requires
>>>>>>> the same thing to be repeated hundreds of times be3fore you ever
>>>>>>> notice
>>>>>>> that it was said once.
>>>>>>
>>>>>> I have not "corrected" anyone on this.  Stop misrepresenting my
>>>>>> position - that's a form of lying, and I would have thought your
>>>>>> religious views would dissuade you from behaving like that, even
>>>>>> inadvertently.  (You must recognise by now that you often
>>>>>> misunderstand the points people are making - so even if /you/
>>>>>> think they are saying one thing, best to avoid telling everyone
>>>>>> else what you /think/ their position is - just say your own ideas
>>>>>> in your own words, and you will avoid getting it wrong.
>>>>>>
>>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>>> meaning of a phrase, discuss and clarify the situation with
>>>>>> Richard - no need to drag 3rd parties into the matter in some kind
>>>>>> of appeal to "authority".
>>>>>>
>>>>>>
>>>>>> Mike.
>>>>>>
>>>>>
>>>>> It is not that case that when N steps of DD are correctly simulated
>>>>> by HH that these N steps are incorrectly simulated on the basis that
>>>>> N+1 could have been simulated.
>>>>>
>>>>> *Although you understand this Richard does not understand this*
>>>>
>>>> It is not a question of "correct understanding".  It's just that
>>>> different people may have slightly different interpretations for the
>>>> scope of a phrase like "correct simulation".
>>>>
>>>> Do you think that Richard thinks the step by step x86 instruction
>>>> emulation part of your code is faulty?  Maybe he does, but I doubt
>>>> that... (and if not we are not disagreeing).  More likely he takes
>>>> "correct simulation" to mean what I'd call "correct full simulation"
>>>> or something.  Perhaps you should sort out the facts you actually
>>>> agree on, then you can move on.
>>>>
>>>>
>>>> Mike.
>>>>
>>>
>>> Richard insists that a correct partial simulation is totally incorrect.
>>>
>>> You insist that either (a) or (b) are incorrect or
>>> that a correct simulation of D by H must incorrectly
>>> emulate the x86 instructions of D or emulate them in
>>> some other order than they are specified.
>>
>> Your simulation skips over the non-halting pattern detection
>> instructions by aborting the simulation before they execute.
>>
>
> *Not so much*
>
> Begin Local Halt Decider Simulation        Execution Trace Stored at:113027
> [00001c42][00113013][00113017] 55          push ebp
> [00001c43][00113013][00113017] 8bec        mov ebp,esp
> [00001c45][0011300f][00102fe3] 51          push ecx
> [00001c46][0011300f][00102fe3] 8b4508      mov eax,[ebp+08] ; DD
> [00001c49][0011300b][00001c42] 50          push eax         ; DD
> [00001c4a][0011300b][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
> [00001c4d][00113007][00001c42] 51          push ecx         ; DD
> [00001c4e][00113003][00001c53] e80ff7ffff  call 00001362    ; HH
> New slave_stack at:14da47

INCORRECT RIGHT HERE.

call 00001362 MUST be followed by the instuction at 00001362, and not
the instuction at 00001c42, as that is what the instruction does.

> [00001c42][0015da3b][0015da3f] 55          push ebp
> [00001c43][0015da3b][0015da3f] 8bec        mov ebp,esp
> [00001c45][0015da37][0014da0b] 51          push ecx
> [00001c46][0015da37][0014da0b] 8b4508      mov eax,[ebp+08] ; DD
> [00001c49][0015da33][00001c42] 50          push eax         ; DD
> [00001c4a][0015da33][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
> [00001c4d][0015da2f][00001c42] 51          push ecx         ; DD
> [00001c4e][0015da2b][00001c53] e80ff7ffff  call 00001362    ; HH
>
> _DD()
> [00001c42] 55         push ebp
> [00001c43] 8bec       mov ebp,esp
> [00001c45] 51         push ecx
> [00001c46] 8b4508     mov eax,[ebp+08] ; DD
> [00001c49] 50         push eax         ; DD
> [00001c4a] 8b4d08     mov ecx,[ebp+08] ; DD
> [00001c4d] 51         push ecx         ; DD
> [00001c4e] e80ff7ffff call 00001362    ; HH
> [00001c53] 83c408     add esp,+08
> [00001c56] 8945fc     mov [ebp-04],eax
> [00001c59] 837dfc00   cmp dword [ebp-04],+00
> [00001c5d] 7402       jz 00001c61
> [00001c5f] ebfe       jmp 00001c5f
> [00001c61] 8b45fc     mov eax,[ebp-04]
> [00001c64] 8be5       mov esp,ebp
> [00001c66] 5d         pop ebp
> [00001c67] c3         ret
> Size in bytes:(0038) [00001c67]
>

Which isn't a complete program, and thus not a valid.