On Friday, January 3, 2003 at 9:19:11 AM UTC+1, Ralf Hildebrandt wrote:
> Hi Clyde!
> [quote repaired]
> >>>Does anything exist in VHDL equivalent to verilog conditional
> >>>compilation directive ( `ifdef .... `else .... `endif )
> >>Just use constants.
> > This does not work in Synplify.... It required a signal.
> This a plain VHDL - this should work everywhere.
> define a constant:
> constant switchA : integer:=1; -- 1 enabled / 0 disabled
>
> Feed this constant through an entitiy to a lower component:
> entity compA is
> generic(
> switchA : integer:=1 );
> port( -- and so on...
> );
> end compA;
>
> Instantiate this component in the top component (where the constat is
> defined).
> Within compA use the constant:
>
> process(in1,in2)
> begin
> if (switchA=1) then
> out1<=in1 AND in2;
> else out1<=in1;
> end if;
> end process;
>
> As you can see - the constant defines, if and AND-gate is inferred or a
> simple wire is taken.
>
> With the uses of constants if have written a several extras for a
> microcontroller, that all can be disabled, if one changes the constant.
> Hint: If you synthesize just compA to test the synthesized components
> within the behavioral top-component, you have to change the default
> value of the constant within the entity AND where the constant is
> defined in the top-component.
>
> Your synthesis tool will warn you, that an expression is never reached.
> (In my examle: the else-statement.)
> Ralf
Hi,
Can anyone say how to address schemes and write a byte code?