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Best approach using GHDL to wrap clocked VHDL

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Subject: Best approach using GHDL to wrap clocked VHDL
From: connolly.damien@gmail.com (Damien Towning)
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by: Damien Towning - Wed, 18 Jan 2023 21:08 UTC

I have a VHDL project. Is a RISC-V Bonfire in an Efinity T-35 FPGA. The board the T-35 is in has external clock on a GPIO pin that is driving it. Runs on the FPGA happily. Now I have successfully built my project using GHDL-GCC. Next I have started looking at wrapping it and am reading through the documentation. But in general what would be best practice for binding the SYSCLK in my VHDL code to some external function to drive it? I have been looking at the customc example where the VHDL calls C functions. Can I call a C function that runs the clock and return a clock step that way? Or have I got this the wrong way around and the C code should reach in to the running object and clock it that way?

Re: Best approach using GHDL to wrap clocked VHDL

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Subject: Re: Best approach using GHDL to wrap clocked VHDL
From: kkjennings@sbcglobal.net (KJ)
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by: KJ - Sun, 22 Jan 2023 17:38 UTC

On Wednesday, January 18, 2023 at 4:08:13 PM UTC-5, connoll...@gmail.com wrote:
> I have a VHDL project. Is a RISC-V Bonfire in an Efinity T-35 FPGA. The board the T-35 is in has external clock on a GPIO pin that is driving it. Runs on the FPGA happily. Now I have successfully built my project using GHDL-GCC. Next I have started looking at wrapping it and am reading through the documentation. But in general what would be best practice for binding the SYSCLK in my VHDL code to some external function to drive it? I have been looking at the customc example where the VHDL calls C functions. Can I call a C function that runs the clock and return a clock step that way? Or have I got this the wrong way around and the C code should reach in to the running object and clock it that way?

I've read this several times and I have no idea what you are trying to do. An example,
> Next I have started looking at wrapping it

What is "it"? Are you trying to do something on the board? In simulation? Who knows...

But since this is a VHDL group, I would suggest that if you are trying to "wrap" your FPGA design for simulation, then the best approach is to write a testbench for your FPGA design. This involves writing VHDL that models all of the inputs to the FPGA and monitors all of the outputs. You would instantiate that FPGA design in the testbench. There would be no reason to use C to do any of this. I would go on but like I said, I have no idea what you're really trying to do, so you need to explain that first.

Kevin Jennings

Do not underestimate the value of print statements for debugging.

devel / comp.lang.vhdl / Re: Best approach using GHDL to wrap clocked VHDL

Subject	Author
Best approach using GHDL to wrap clocked VHDL	Damien Towning
Best approach using GHDL to wrap clocked VHDL	KJ