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devel / comp.lang.vhdl / Mod 6 counter using Mod 8 counter

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o Mod 6 counter using Mod 8 counterNAVIN PRASATH.M ECE

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Mod 6 counter using Mod 8 counter

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Subject: Mod 6 counter using Mod 8 counter
From: 1911010@nec.edu.in (NAVIN PRASATH.M ECE)
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 by: NAVIN PRASATH.M ECE - Thu, 21 Sep 2023 01:52 UTC

I am trying to implement mod 6 counter using mod 8 counter with JK Flipflop but the output waveform is not correct as required.What is the mistake in my code?

module mod_six_counter(clk,rst,q,qbar);
input clk;
input wire rst;
output wire [2:0]q;
output [2:0]qbar;
assign rst = ~((~qbar[0])&qbar[1]&(qbar[2]));
jkff ff1(1'b1,1'b1,clk,rst,q[0],qbar[0]);
jkff ff2(1'b1,1'b1,qbar[0],rst,q[1],qbar[1]);
jkff ff3(1'b1,1'b1,qbar[1],rst,q[2],qbar[2]);

endmodule

module jkff(j,k,clk,rst,q,qbar);
input j,k,clk,rst;
output reg q;
output qbar;
always@(posedge clk or negedge rst)
begin
if (!rst) q <= 1'b0;
else begin
case({j,k})
2'b00 : q<=q;
2'b01 : q<=1'b0;
2'b10 : q<=1'b1;
2'b11 : q<=~q;
endcase
end
end
assign qbar = ~q;
endmodule

TestBench Code :

module tbmod_sixcounter;
reg clk,rst;
wire[2:0] q,qbar;
mod_six_counter DUT(.clk(clk),.rst(rst),.q(q),.qbar(qbar));
always #10 clk=~clk;
initial
begin
clk<=0;
rst<=0;
#7 rst<=1;

end
endmodule


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