One of my VHDL textbooks does not mention VHDL Blocks at all, the other
grudgingly admits to their existence but recommends against using them.
One online advice respondent says "never use blocks".

I like VHDL blocks and use them all the time.

1. They help me organize long files and let me reuse common names.
For example, a large architecture might have 3 or 4 state machines. I
write boilerplate state machine code with "type state_t is (...);" and
"signal state, next_state : state_t:", with each state machine in its
own block. You don't have to invent new names. On the other hand, you
must give blocks names: choose informative names and it helps with
documentation.

2. My editor notepad++ handles blocks nicely. I can "collapse" blocks
to navigate within files easily.

3. The Xilinx default simulator hierarchy viewer handles blocks nicely.
When I hover over a signal in the waveform viewer, the tooltip tells
my what block the signal is in.

I agree with the common advice to not use blocks when component
instantiations would be more appropriate.