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devel / comp.lang.forth / Re: BugsBoard: an FPGA design for the Digilent Cmod S7

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o Re: BugsBoard: an FPGA design for the Digilent Cmod S7Hugh Aguilar

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Re: BugsBoard: an FPGA design for the Digilent Cmod S7

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Subject: Re: BugsBoard: an FPGA design for the Digilent Cmod S7
From: hughaguilar96@gmail.com (Hugh Aguilar)
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 by: Hugh Aguilar - Mon, 21 Aug 2023 02:08 UTC

On Sunday, August 20, 2023 at 6:35:21 PM UTC-7, Myron Plichota wrote:
> I wish that clf culture relaxed a wee bit and became famous for promoting
> the merits of fundamental Forth programming precepts.

I remember that I told you about Testra's MiniForth built on the Lattice
isp1048 PLD in 1995 and how it held the data-stack in external memory.
My processor design also holds the data-stack in memory (internal now).
You said that myself and everybody at Testra should take a Programming-101
class to learn basic programming concepts. You seem to think that the only
viable solution for a Forth processor is to hold the entire data-stack in
cell flip-flops so that Forth words such as DUP SWAP OVER + etc. can be
single clock-cycle. The data-stack would be fairly small, like 8 elements.
There are actually serious problems with this technique. For one thing,
you can't have ISRs because you have no way to save/restore the Forth context.
I think that you could really relax a wee bit too --- dial down the arrogance!

The MiniForth was used in a a motion-control board that was less-expensive
and higher-performing than the competition's motion-control board that used
an MC68000 programmed in C. Has the Bugs18 processor ever competed
successfully with C? Has it ever been used in a real-world application?
This is the year 2023 --- the MiniForth came out in 1995 --- nobody in the
Forth community has come up with anything comparable after three decades.

Your Bugs18 has a 6-bit opcode, so there are 64 instructions.
That is not very many! There is no future in a processor with only 64
instructions --- this is a toy --- it will never be used for real-world applications.

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