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devel / comp.lang.forth / Re: BugsBoard: an FPGA design for the Digilent Cmod S7

Re: BugsBoard: an FPGA design for the Digilent Cmod S7

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https://news.novabbs.org/devel/article-flat.php?id=24356&group=comp.lang.forth#24356

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Subject: Re: BugsBoard: an FPGA design for the Digilent Cmod S7
From: gnuarm.deletethisbit@gmail.com (Lorem Ipsum)
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by: Lorem Ipsum - Mon, 21 Aug 2023 04:27 UTC

On Sunday, August 20, 2023 at 10:09:02 PM UTC-4, Hugh Aguilar wrote:
> On Sunday, August 20, 2023 at 6:35:21 PM UTC-7, Myron Plichota wrote:
> > I wish that clf culture relaxed a wee bit and became famous for promoting
> > the merits of fundamental Forth programming precepts.
> I remember that I told you about Testra's MiniForth built on the Lattice
> isp1048 PLD in 1995 and how it held the data-stack in external memory.
> My processor design also holds the data-stack in memory (internal now).
> You said that myself and everybody at Testra should take a Programming-101
> class to learn basic programming concepts. You seem to think that the only
> viable solution for a Forth processor is to hold the entire data-stack in
> cell flip-flops so that Forth words such as DUP SWAP OVER + etc. can be
> single clock-cycle.

Using distributed RAM or "cell FFs" is not required for single cycle instructions. The BRAM available in most FPGA allow two port access, where one can read and the other write if that is required. But most stack CPU designers keep the top of stack in a register anyway, and often the next on stack as well. So, technically these are "cell FFs", but only for the top and possibly next to top of stack. But they are not required. Dual access can provide two reads and one write on the same clock cycle.

> The data-stack would be fairly small, like 8 elements.
> There are actually serious problems with this technique. For one thing,
> you can't have ISRs because you have no way to save/restore the Forth context.
> I think that you could really relax a wee bit too --- dial down the arrogance!
>
> The MiniForth was used in a a motion-control board that was less-expensive
> and higher-performing than the competition's motion-control board that used
> an MC68000 programmed in C. Has the Bugs18 processor ever competed
> successfully with C? Has it ever been used in a real-world application?
> This is the year 2023 --- the MiniForth came out in 1995 --- nobody in the
> Forth community has come up with anything comparable after three decades.

Mostly because the MiniForth is a specialized processor. Not so many designers want to mess with the issues of using such a processor, when they can use off the shelf processors to do the job.

> Your Bugs18 has a 6-bit opcode, so there are 64 instructions.
> That is not very many! There is no future in a processor with only 64
> instructions --- this is a toy --- it will never be used for real-world applications.

??? There are a number of stack processors with 5 bit instructions which are used in volume applications in ASICs. I believe the b16 is one of those.. Or maybe the instructions are 4 bits, I don't recall.

Why can't stack processors with small instructions be useful in real world applications?

Rick C.

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Subject	Author
Re: BugsBoard: an FPGA design for the Digilent Cmod S7	Lorem Ipsum