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devel / comp.lang.forth / Re: BugsBoard: an FPGA design for the Digilent Cmod S7

Re: BugsBoard: an FPGA design for the Digilent Cmod S7

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https://news.novabbs.org/devel/article-flat.php?id=24361&group=comp.lang.forth#24361

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Subject: Re: BugsBoard: an FPGA design for the Digilent Cmod S7
From: gnuarm.deletethisbit@gmail.com (Lorem Ipsum)
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by: Lorem Ipsum - Mon, 21 Aug 2023 07:45 UTC

On Monday, August 21, 2023 at 1:48:44 AM UTC-4, Myron Plichota wrote:
> > Is your processor single clock per instruction? What is the max clock rate?
> Yes. A modest 48 MHz.

That's a promising capability. I recall a couple of families of audio processors for hearing aids, that were just designed to handle the signal processing, such as filters. The architecture was a linear set of instructions, which might have had some looping capability (hard to think it wouldn't). It was designed to capture an ADC sample and run through the code once, lather, rinse, repeat.

I never obtained details of the instructions or architecture, because the makers were mainly interested in large buyer. My production quantities range around 1,000 to 3,000 units per year these days, not enough to interest these guys.

I always appealed to me. They were pretty low power and clearly optimized for audio work. One supplier was ADI. I took a quick look, and the units I had seen seem to be out of date now. Here's one that's pretty powerful.

https://www.onsemi.com/download/data-sheet/pdf/e7111-d.pdf

There's lots of stuff on the market.

Rick C.

+++ Get 1,000 miles of free Supercharging
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Subject	Author
Re: BugsBoard: an FPGA design for the Digilent Cmod S7	Lorem Ipsum