Rocksolid Light - comp.lang.forth - Re: BugsBoard: an FPGA design for the Digilent Cmod S7

Re: BugsBoard: an FPGA design for the Digilent Cmod S7

<f647d353-bb8c-4d20-ab8a-ef8d3f3135f6n@googlegroups.com>

https://news.novabbs.org/devel/article-flat.php?id=24364&group=comp.lang.forth#24364

X-Received: by 2002:a05:620a:6795:b0:76d:929a:c94d with SMTP id rr21-20020a05620a679500b0076d929ac94dmr29676qkn.1.1692611118498; Mon, 21 Aug 2023 02:45:18 -0700 (PDT)
X-Received: by 2002:a17:902:cecc:b0:1bc:6799:3f88 with SMTP id d12-20020a170902cecc00b001bc67993f88mr2788236plg.0.1692611117894; Mon, 21 Aug 2023 02:45:17 -0700 (PDT)
Path: i2pn2.org!i2pn.org!usenet.blueworldhosting.com!diablo1.usenet.blueworldhosting.com!feeder.usenetexpress.com!tr3.iad1.usenetexpress.com!69.80.99.11.MISMATCH!border-1.nntp.ord.giganews.com!nntp.giganews.com!news-out.google.com!nntp.google.com!postnews.google.com!google-groups.googlegroups.com!not-for-mail
Newsgroups: comp.lang.forth
Date: Mon, 21 Aug 2023 02:45:17 -0700 (PDT)
In-Reply-To: <5e6519d2-f054-4d38-af40-16163c298e5fn@googlegroups.com>
Injection-Info: google-groups.googlegroups.com; posting-host=199.48.66.218; posting-account=zkoivgoAAABqROvHfKJPu3S9NWXITnSr
NNTP-Posting-Host: 199.48.66.218
References: <97d644a8-d38f-49b0-b73e-45ae276d327fn@googlegroups.com> <f37bb625-4a7b-417f-b331-1c75c20cadbdn@googlegroups.com> <ad6b7a42-b48a-44b2-8dee-6b250161fb72n@googlegroups.com> <c5ab525b-df41-4a21-a734-3333f692dea3n@googlegroups.com> <d396919a-3d60-409c-ba9f-aa89a5b410dcn@googlegroups.com> <e2f97697-6534-488d-97e7-d932a0ef1a16n@googlegroups.com> <2068cfb8-d4bd-4c35-8002-a6b807521ca4n@googlegroups.com> <477a6440-e585-485a-87f3-ff68949f720fn@googlegroups.com> <1c22a136-2767-44fe-9c2b-40326c2e5ce1n@googlegroups.com> <00e5889f-0afc-463a-a3f8-e10b6599ba41n@googlegroups.com> <c9f0b14c-bfb8-483e-b4f4-145007933b5dn@googlegroups.com> <a7f76113-b961-4b1f-b523-bcf6a19f9239n@googlegroups.com> <b8411641-e13d-46b7-adaf-52690a50b84dn@googlegroups.com> <baca9a0d-3253-43e0-9080-07274f32a3b0n@googlegroups.com> <732f634c-1498-4cd6-a9b3-46fd26fc2405n@googlegroups.com> <39c9cbed-24d0-4b4c-ae6b-403e7c799520n@googlegroups.com> <b52a36fb-a807-4270-95b5-3b4b0129b6f2n@googlegroups.com> <1061e4f2-f995-4860-8e1b-ddd95cfcc13dn@googlegroups.com> <ec4595e2-a4d5-4ec8-b5b8-f9ec461cdc7bn@googlegroups.com> <dce894bc-5679-474b-9b46-d7e6f0ef6ff0n@googlegroups.com> <6df3230c-e064-4a19-8489-658dd582d44fn@googlegr
oups.com> <ce9ec607-3bba-4903-aba9-469f664be8bcn@googlegroups.com> <423abade-eb1f-4617-a8e2-bc85add3f014n@googlegroups.com> <71e2c9ed-aa2c-4297-916b-686db8e2d12dn@googlegroups.com> <96374ae4-32d7-4bec-8ad4-cc82d9e914e9n@googlegroups.com> <b83fdf09-07dd-4639-8755-d08aa7372375n@googlegroups.com> <3b5b4b78-7e09-4197-a7e4-f7bb2b556300n@googlegroups.com> <05cae420-7df8-4a14-9c95-3218e39a052en@googlegroups.com> <59a6db96-913f-4217-bc0f-a936eab183bcn@googlegroups.com> <fc67c604-6c4f-43c3-85f9-fc6947930893n@googlegroups.com> <87d9ffd6-324d-4b1d-96b1-abb98ecf2063n@googlegroups.com> <62d81e1c-a529-4b86-9b6c-0b15f719c471n@googlegroups.com> <fd1aeb80-d11a-4a52-bff7-500b914c951an@googlegroups.com> <3faed891-7cca-4289-b5a3-0696d49d62een@googlegroups.com> <c360f152-25d9-4ded-91c3-005876d6f16cn@googlegroups.com> <d1d36b2c-e918-4e1c-a72b-05ee62171d9cn@googlegroups.com> <5e6519d2-f054-4d38-af40-16163c298e5fn@googlegroups.com>
User-Agent: G2/1.0
MIME-Version: 1.0
Message-ID: <f647d353-bb8c-4d20-ab8a-ef8d3f3135f6n@googlegroups.com>
Subject: Re: BugsBoard: an FPGA design for the Digilent Cmod S7
From: myronplichota@gmail.com (Myron Plichota)
Injection-Date: Mon, 21 Aug 2023 09:45:18 +0000
Content-Type: text/plain; charset="UTF-8"
Content-Transfer-Encoding: quoted-printable
Lines: 30

by: Myron Plichota - Mon, 21 Aug 2023 09:45 UTC

On Monday, August 21, 2023 at 3:45:25 AM UTC-4, Lorem Ipsum wrote:
> On Monday, August 21, 2023 at 1:48:44 AM UTC-4, Myron Plichota wrote:
> > > Is your processor single clock per instruction? What is the max clock rate?
> > Yes. A modest 48 MHz.
> That's a promising capability. I recall a couple of families of audio processors for hearing aids, that were just designed to handle the signal processing, such as filters. The architecture was a linear set of instructions, which might have had some looping capability (hard to think it wouldn't). It was designed to capture an ADC sample and run through the code once, lather, rinse, repeat.
>
> I never obtained details of the instructions or architecture, because the makers were mainly interested in large buyer. My production quantities range around 1,000 to 3,000 units per year these days, not enough to interest these guys.
>
> I always appealed to me. They were pretty low power and clearly optimized for audio work. One supplier was ADI. I took a quick look, and the units I had seen seem to be out of date now. Here's one that's pretty powerful.
>
> https://www.onsemi.com/download/data-sheet/pdf/e7111-d.pdf
>
> There's lots of stuff on the market.

Nothing beats an ASIC for a theoretical market advantage. BugsBoard can only offer a user with a high-performance platform that enlists the Python3 front end to generate code for the underlying Forth CPU (that lo and behold, does not suck at DSP algorithms). My question to anyone reading this is: Would you want your daughter to marry a BugsBoard programmer in these times?

I can't drive 55.

devel / comp.lang.forth / Re: BugsBoard: an FPGA design for the Digilent Cmod S7

Subject	Author
Re: BugsBoard: an FPGA design for the Digilent Cmod S7	Myron Plichota