Hi,
I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop.
Here is my code :
module D_to_jk(j,k,clk,rst,q);
input j,k,clk,rst;
output reg q;
wire w1,w2,w3,w4;
wire q_bar;
assign w1=~k;
assign q_bar= ~q;
assign w2= j&q_bar;
assign w3= w1&q;
assign w4= w2|w3;
D d(w4,clk,rst,q);
endmodule

Please point me out the error so that I may rectify.
Thanks
Indrayudh

On 6/9/23 6:44 AM, Indrayudh Nandy wrote:
> Hi,
> I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop.
> Here is my code :
> module D_to_jk(j,k,clk,rst,q);
> input j,k,clk,rst;
> output reg q;
> wire w1,w2,w3,w4;
> wire q_bar;
> assign w1=~k;
> assign q_bar= ~q;
> assign w2= j&q_bar;
> assign w3= w1&q;
> assign w4= w2|w3;
> D d(w4,clk,rst,q);
> endmodule
>
> Please point me out the error so that I may rectify.
> Thanks
> Indrayudh

YOUR q needs to be a wire which you are connecting to the actual reg
which will be in the D primative.

On Friday, June 9, 2023 at 6:44:18 AM UTC-4, Indrayudh Nandy wrote:
> Hi,
> I am facing this error in vivado while writing a code for conversion of D flip flop to JK flip flop.
> Here is my code :
> module D_to_jk(j,k,clk,rst,q);
> input j,k,clk,rst;
> output reg q;
> wire w1,w2,w3,w4;
> wire q_bar;
> assign w1=~k;
> assign q_bar= ~q;
> assign w2= j&q_bar;
> assign w3= w1&q;
> assign w4= w2|w3;
> D d(w4,clk,rst,q);
> endmodule
>
> Please point me out the error so that I may rectify.
> Thanks
> Indrayudh

I think your biggest error, is trying to compile a Verilog program with a VHDL tool, perhaps?

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Rick C.

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