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devel / comp.lang.vhdl / Re: Converting Signed (or unsigned) to TO_INTEGER

Re: Converting Signed (or unsigned) to TO_INTEGER

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https://news.novabbs.org/devel/article-flat.php?id=97&group=comp.lang.vhdl#97

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Date: Thu, 16 Mar 2023 17:33:54 -0700 (PDT)
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Subject: Re: Converting Signed (or unsigned) to TO_INTEGER
From: kkjennings@sbcglobal.net (KJ)
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by: KJ - Fri, 17 Mar 2023 00:33 UTC

On Thursday, March 16, 2023 at 12:16:09 PM UTC-4, A “Ashvin” wrote:
> I have the following declarations
>
> signal S: SIGNED(7 downto 0);
> signal N: INTEGER;
>
> N <= TO_INTEGER(S);
>
> Question: Will the TO_INTEGER functiona sign extend 'S' to 32 bit integer?
>
> Thanks.

VHDL integers are not a collection of 'bits' so in that sense the answer to your question is 'No'. However, if you assign S <= "11111111"; then N will be set to -1 in your example. I assume this is more along the lines of the real question you are getting at. Commonly, VHDL integers are implemented as either 32 or 64 bits.

If you have access to a VHDL simulator, it seems like you could have answered this question yourself with about the same amount of effort you put into your post...is there a reason you didn't? Or do you not have access to a VHDL simulator? If not, I suggest at least GHDL which is free for download..

Kevin Jennings

Subject	Author
Converting Signed (or unsigned) to TO_INTEGER	KJ