On Tuesday, September 5, 2023 at 4:36:49 AM UTC+9, Paul A. Clayton wrote:
> Manual layout is possible?
Manual placement and routing are possible but its very harder than ASICs (floor planner is supported), some student implemented 700MHz configuration (max freq on DSP block is around 700).

Anyway, many RISC-V cores are developed as a hobby for FPGAs including tiny FPGAs.

And google supports an open-source hardware that your ASIC chip can be implemented without charge (supporting GF 130nm process, but limited #of pins and area) under condition of fully opened-source.

Best,
S.Takano

On Tuesday, September 5, 2023 at 4:36:49 AM UTC+9, Paul A. Clayton wrote:
> (I suspect explaining the abilities and limitations abstractly to
> one who has no FPGA programming experience would be difficult;
> complete unfamiliarity with the tools and techniques introduces a
> communication barrier. "Explain it like I am five years old"
> coupled with "so I could do a Master's thesis around it next year"
> is probably not a reasonable expectation.☺ That people use their
> time to explain technical matters — for free — is admirable, yet
> people have biological (and more specifically human) needs.
> Admiring someone correlates with concern for their well-being.)

No problem, that is "otagai-sama" :)

Regards,
S.Takano

On Monday, September 4, 2023 at 6:06:44 PM UTC+1, Paul A. Clayton wrote:
> On 8/30/23 1:42 PM, JimBrakefield wrote:
> [snip]
> > Another person in this arena is Jan Gray, https://fpga.org/ and more recently: https://github.com/grayresearch
> > who does hand layout of his FPGA cores for maximum speed/minimal LUT count.
> Manual layout is possible? From the little I have read, I thought
> the FPGA configuration bitstreams used a non-disclosed format and
> the FPGA vendor tools did not provide such specific control. My
> "knowledge" about FPGAs is very limited.

Project-Xray performs monte-carlo program generation for FPGAs
such that the internal layout may be 100% deduced.

this has resulted in nextpnr-xilinx and nextpnr-ecp5 providing
near-100% of the functionality of Vivado and Trellis respectively...
except for the "GUI Wizards" and support for more than one
asynchronous clock domain routing. (you can use the *same*
PLL and say divide it by 100 on one hand and 27 on the other
and do async-domain-crossing using SFF-chains as usual,
but if you try *two* separate PLLs then nexpnr just can't cope)

other than that they're pretty f*****g good, and routing is
comparatively up-to-speed. Symbiflow on the other hand
is awful (7x slower)

l.