On 1/18/24 22:05, olcott wrote:
> On 1/18/2024 2:42 PM, immibis wrote:
>> On 1/18/24 21:03, olcott wrote:
>>> On 1/18/2024 1:46 PM, immibis wrote:
>>>> On 1/18/24 20:30, olcott wrote:
>>>>> On 1/18/2024 1:19 PM, immibis wrote:
>>>>>> On 1/18/24 20:05, olcott wrote:
>>>>>>> On 1/18/2024 11:55 AM, Mike Terry wrote:
>>>>>>>> On 18/01/2024 17:15, olcott wrote:
>>>>>>>>> On 1/18/2024 10:37 AM, Mike Terry wrote:
>>>>>>>>>> On 18/01/2024 14:47, olcott wrote:
>>>>>>>>>>> On 1/18/2024 6:24 AM, Richard Damon wrote:
>>>>>>>>>>>> On 1/17/24 11:35 PM, olcott wrote:
>>>>>>>>>>>>> *This is true on the basis of the meaning of its words*
>>>>>>>>>>>>>
>>>>>>>>>>>>> The ultimate measure [of a correct simulation] is the
>>>>>>>>>>>>> correct x86
>>>>>>>>>>>>> emulation of the x86 instructions in the order that they
>>>>>>>>>>>>> are specified.
>>>>>>>>>>>>
>>>>>>>>>>>> And continuing until it finishes. (since the question is
>>>>>>>>>>>> DOES it finish).
>>>>>>>>>>>
>>>>>>>>>>> (a) If simulating termination analyzer H correctly determines
>>>>>>>>>>> that D
>>>>>>>>>>> correctly simulated by H cannot possibly reach its own
>>>>>>>>>>> simulated final
>>>>>>>>>>> state and terminate normally then
>>>>>>>>>>>
>>>>>>>>>>> (b) H can abort its simulation of D and correctly report that
>>>>>>>>>>> D specifies a non-halting sequence of configurations.
>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>>>
>>>>>>>>>>>>> The alternative is incorrectly emulating the x86
>>>>>>>>>>>>> instructions in some
>>>>>>>>>>>>> other order than they are specified.
>>>>>>>>>>>>>
>>>>>>>>>>>>
>>>>>>>>>>>> No, you are neglecting that partial simulation is incorrect.
>>>>>>>>>>>
>>>>>>>>>>> Mike Terry has corrected you on this many times yet your ADD
>>>>>>>>>>> requires
>>>>>>>>>>> the same thing to be repeated hundreds of times be3fore you
>>>>>>>>>>> ever notice
>>>>>>>>>>> that it was said once.
>>>>>>>>>>
>>>>>>>>>> I have not "corrected" anyone on this.  Stop misrepresenting
>>>>>>>>>> my position - that's a form of lying, and I would have thought
>>>>>>>>>> your religious views would dissuade you from behaving like
>>>>>>>>>> that, even inadvertently.  (You must recognise by now that you
>>>>>>>>>> often misunderstand the points people are making - so even if
>>>>>>>>>> /you/ think they are saying one thing, best to avoid telling
>>>>>>>>>> everyone else what you /think/ their position is - just say
>>>>>>>>>> your own ideas in your own words, and you will avoid getting
>>>>>>>>>> it wrong.
>>>>>>>>>>
>>>>>>>>>> Additionally, even if I had "corrected" Richard many times, SO
>>>>>>>>>> WHAT? If you and Richard have some disagreement over the exact
>>>>>>>>>> meaning of a phrase, discuss and clarify the situation with
>>>>>>>>>> Richard - no need to drag 3rd parties into the matter in some
>>>>>>>>>> kind of appeal to "authority".
>>>>>>>>>>
>>>>>>>>>>
>>>>>>>>>> Mike.
>>>>>>>>>>
>>>>>>>>>
>>>>>>>>> It is not that case that when N steps of DD are correctly
>>>>>>>>> simulated
>>>>>>>>> by HH that these N steps are incorrectly simulated on the basis
>>>>>>>>> that
>>>>>>>>> N+1 could have been simulated.
>>>>>>>>>
>>>>>>>>> *Although you understand this Richard does not understand this*
>>>>>>>>
>>>>>>>> It is not a question of "correct understanding".  It's just that
>>>>>>>> different people may have slightly different interpretations for
>>>>>>>> the scope of a phrase like "correct simulation".
>>>>>>>>
>>>>>>>> Do you think that Richard thinks the step by step x86
>>>>>>>> instruction emulation part of your code is faulty?  Maybe he
>>>>>>>> does, but I doubt that... (and if not we are not disagreeing).
>>>>>>>> More likely he takes "correct simulation" to mean what I'd call
>>>>>>>> "correct full simulation" or something.  Perhaps you should sort
>>>>>>>> out the facts you actually agree on, then you can move on.
>>>>>>>>
>>>>>>>>
>>>>>>>> Mike.
>>>>>>>>
>>>>>>>
>>>>>>> Richard insists that a correct partial simulation is totally
>>>>>>> incorrect.
>>>>>>>
>>>>>>> You insist that either (a) or (b) are incorrect or
>>>>>>> that a correct simulation of D by H must incorrectly
>>>>>>> emulate the x86 instructions of D or emulate them in
>>>>>>> some other order than they are specified.
>>>>>>
>>>>>> Your simulation skips over the non-halting pattern detection
>>>>>> instructions by aborting the simulation before they execute.
>>>>>>
>>>>>
>>>>> *Not so much*
>>>>>
>>>>> Begin Local Halt Decider Simulation        Execution Trace Stored
>>>>> at:113027
>>>>> [00001c42][00113013][00113017] 55          push ebp
>>>>> [00001c43][00113013][00113017] 8bec        mov ebp,esp
>>>>> [00001c45][0011300f][00102fe3] 51          push ecx
>>>>> [00001c46][0011300f][00102fe3] 8b4508      mov eax,[ebp+08] ; DD
>>>>> [00001c49][0011300b][00001c42] 50          push eax         ; DD
>>>>> [00001c4a][0011300b][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>>>> [00001c4d][00113007][00001c42] 51          push ecx         ; DD
>>>>> [00001c4e][00113003][00001c53] e80ff7ffff  call 00001362    ; HH
>>>>> New slave_stack at:14da47
>>>>> [00001c42][0015da3b][0015da3f] 55          push ebp
>>>>> [00001c43][0015da3b][0015da3f] 8bec        mov ebp,esp
>>>>> [00001c45][0015da37][0014da0b] 51          push ecx
>>>>> [00001c46][0015da37][0014da0b] 8b4508      mov eax,[ebp+08] ; DD
>>>>> [00001c49][0015da33][00001c42] 50          push eax         ; DD
>>>>> [00001c4a][0015da33][00001c42] 8b4d08      mov ecx,[ebp+08] ; DD
>>>>> [00001c4d][0015da2f][00001c42] 51          push ecx         ; DD
>>>>> [00001c4e][0015da2b][00001c53] e80ff7ffff  call 00001362    ; HH
>>>>>
>>>>> _DD()
>>>>> [00001c42] 55         push ebp
>>>>> [00001c43] 8bec       mov ebp,esp
>>>>> [00001c45] 51         push ecx
>>>>> [00001c46] 8b4508     mov eax,[ebp+08] ; DD
>>>>> [00001c49] 50         push eax         ; DD
>>>>> [00001c4a] 8b4d08     mov ecx,[ebp+08] ; DD
>>>>> [00001c4d] 51         push ecx         ; DD
>>>>> [00001c4e] e80ff7ffff call 00001362    ; HH
>>>>> [00001c53] 83c408     add esp,+08
>>>>> [00001c56] 8945fc     mov [ebp-04],eax
>>>>> [00001c59] 837dfc00   cmp dword [ebp-04],+00
>>>>> [00001c5d] 7402       jz 00001c61
>>>>> [00001c5f] ebfe       jmp 00001c5f
>>>>> [00001c61] 8b45fc     mov eax,[ebp-04]
>>>>> [00001c64] 8be5       mov esp,ebp
>>>>> [00001c66] 5d         pop ebp
>>>>> [00001c67] c3         ret
>>>>> Size in bytes:(0038) [00001c67]
>>>>>
>>>>
>>>> Where is the non-halting pattern detection being simulated?
>>>
>>> repeating instructions [00001c42] to [00001c4e]
>>>
>> Which instruction detects non-halting patterns?
>
> First of all can you see that this sequence repeats?
>

First of all can you see this sequence skips over instructions which are
present in the program?