On Saturday, July 22, 2023 at 10:09:13 PM UTC-4, dxforth wrote:
> On 23/07/2023 10:37 am, Lorem Ipsum wrote:
> > On Saturday, July 22, 2023 at 4:04:49 PM UTC-4, Jurgen Pitaske wrote:
> >> Forth2020 I think is the one you mean, it is to my knowledge the restricted Peter Fucking group - not the one I mentioned.
> >> I have never been there so I do not know them and actually I do not want to know.
> >
> > One of the few things we seem to agree on.
> >
> > I believe the 2020 group is the one that has, in the name of maintaining Win32Forth, rewritten it to suit his purposes. Win32Forth is a useful tool, but has lost all support. It used to have a Yahoo group, with lots of archived info, but Verizon seems to have ended group support. I believe I started a similar group at groups.io, but it gets very little activity.
> >
> IIRC the forth promoted was based on SP-Forth and closed-source. Can't seem
> to find any current links so may no longer be promoted. Main attraction of the
> group today appears to be their Zoom meetings and presentations often by well-
> known Forth personalities.

I don't recall the group. I just remember it was a self appointed team with Peter Forth. Maybe they started modifying Win32Forth, because it has problems with false positives on anti-virus software. I suppose they got in over their heads and switched to some other code base. Don't know.

--

Rick C.

+-- Get 1,000 miles of free Supercharging
+-- Tesla referral code - https://ts.la/richard11209

On Saturday, July 22, 2023 at 6:49:05 PM UTC-7, Dave McGuire wrote:
> On 7/22/23 15:01, Lorem Ipsum wrote:
> >> I would suggest you ceck with one of the Forth facebook groups.
> >> There you can find probably more help and in a friendy way.
> >> https://www.facebook.com/groups/PROGRAMMINGFORTH
> >
> > Just be careful which group you go with. Some are more friendly than others. A guy who goes by Peter Forth (not his real name) has banned several people from his group.
> Interesting! Peter Forth (whatever his real name may be) has never
> been anything other than nice and friendly to me, where YOU have never
> been anything other than a dick.
>
> Every newsgroup has their armchair expert, wannabe authority troll.
> I'm glad I found this one's early before making any friends here.
>
> *PLONK*

I haven't responded to Rick Collins in many years.
I wondered how long it would take you to plonk him --- two days ---
those are two days of your life that have been stolen from you,
just like getting your life blood sucked out by a vampire. lol

In regard to the GA144, when I first heard of it about
two decades ago, my first thought was that all of that parallel
processing was being used for encryption cracking. If this is
the purpose of the chingadera, Charles Moore is obviously not
going to tell you. lol Good luck on figuring out something useful
to do with it --- you could be the first --- at least you could have
fun with it and get experience with something very off-beat.

I wrote an encryption-cracking program a long time ago:
https://groups.google.com/g/comp.lang.forth/c/wP5nw1ClzsM/m/p-At6TDYAQAJ
Reading this thread will give you an idea of what c.l.f. is all about! lol
My program didn't work very well because my evaluation algorithm
wasn't telling me correctly if my bit was 1 or 0 more than 50% of the time.
My code worked; there weren't any bugs --- I just don't think that
I was on the right track --- I haven't done anything with encryption-
cracking since then (that subject is really over my head).

On 23/07/2023 12:51 pm, Lorem Ipsum wrote:
> On Saturday, July 22, 2023 at 10:09:13 PM UTC-4, dxforth wrote:
>> On 23/07/2023 10:37 am, Lorem Ipsum wrote:
>>> On Saturday, July 22, 2023 at 4:04:49 PM UTC-4, Jurgen Pitaske wrote:
>>>> Forth2020 I think is the one you mean, it is to my knowledge the restricted Peter Fucking group - not the one I mentioned.
>>>> I have never been there so I do not know them and actually I do not want to know.
>>>
>>> One of the few things we seem to agree on.
>>>
>>> I believe the 2020 group is the one that has, in the name of maintaining Win32Forth, rewritten it to suit his purposes. Win32Forth is a useful tool, but has lost all support. It used to have a Yahoo group, with lots of archived info, but Verizon seems to have ended group support. I believe I started a similar group at groups.io, but it gets very little activity.
>>>
>> IIRC the forth promoted was based on SP-Forth and closed-source. Can't seem
>> to find any current links so may no longer be promoted. Main attraction of the
>> group today appears to be their Zoom meetings and presentations often by well-
>> known Forth personalities.
>
> I don't recall the group. I just remember it was a self appointed team with Peter Forth. Maybe they started modifying Win32Forth, because it has problems with false positives on anti-virus software. I suppose they got in over their heads and switched to some other code base. Don't know.
>

Found it's hosted below along with the source. I recall the website mentioning
Win32Forth anti-virus issues and avoiding it for that reason.

https://github.com/PeterForth

On Saturday, July 22, 2023 at 11:56:24 PM UTC-4, dxforth wrote:
> On 23/07/2023 12:51 pm, Lorem Ipsum wrote:
> > On Saturday, July 22, 2023 at 10:09:13 PM UTC-4, dxforth wrote:
> >> On 23/07/2023 10:37 am, Lorem Ipsum wrote:
> >>> On Saturday, July 22, 2023 at 4:04:49 PM UTC-4, Jurgen Pitaske wrote:
> >>>> Forth2020 I think is the one you mean, it is to my knowledge the restricted Peter Fucking group - not the one I mentioned.
> >>>> I have never been there so I do not know them and actually I do not want to know.
> >>>
> >>> One of the few things we seem to agree on.
> >>>
> >>> I believe the 2020 group is the one that has, in the name of maintaining Win32Forth, rewritten it to suit his purposes. Win32Forth is a useful tool, but has lost all support. It used to have a Yahoo group, with lots of archived info, but Verizon seems to have ended group support. I believe I started a similar group at groups.io, but it gets very little activity.
> >>>
> >> IIRC the forth promoted was based on SP-Forth and closed-source. Can't seem
> >> to find any current links so may no longer be promoted. Main attraction of the
> >> group today appears to be their Zoom meetings and presentations often by well-
> >> known Forth personalities.
> >
> > I don't recall the group. I just remember it was a self appointed team with Peter Forth. Maybe they started modifying Win32Forth, because it has problems with false positives on anti-virus software. I suppose they got in over their heads and switched to some other code base. Don't know.
> >
> Found it's hosted below along with the source. I recall the website mentioning
> Win32Forth anti-virus issues and avoiding it for that reason.
>
> https://github.com/PeterForth

It's a bit inconvenient. The AVS wants to remove it and it has to be white flagged. Funny that they said they were going to fix it, but never did.

I found reactos-win32forth-repo, which says it's Win32Forth, installed through "Virtual Box from Oracle". It claims to be v6.15, but no virus warnings. Not sure what he did, but 6.15 absolutely does give virus warnings until you white list it. So, I'm not sure what his v6.15 really is. Maybe running in the virtual machine prevents the virus warnings. I wonder what else it blocks. My Win32Forth app uses both serial ports and Winsock. It might be a problem with this installation.

--

Rick C.

+-+ Get 1,000 miles of free Supercharging
+-+ Tesla referral code - https://ts.la/richard11209

Dave McGuire <mcguire@lssmuseum.org> writes:

> Once again, the software is available. I didn't ask about that here
> because I found it already and have judged it to be sufficient for
> my needs.

Those?

https://github.com/mschuldt/ga-tools
https://github.com/mschuldt/ga144-sim

> What I want to do is BUILD A DAMN BOARD.

You have seen that one?

https://hackaday.io/project/163652-ga144-evaluation-board

--
comp.lang.forth - Usenet's best soap opera?

On Sunday, 23 July 2023 at 06:10:24 UTC+1, yeti wrote:
> Dave McGuire <mcg...@lssmuseum.org> writes:
>
> > Once again, the software is available. I didn't ask about that here
> > because I found it already and have judged it to be sufficient for
> > my needs.
> Those?
>
> https://github.com/mschuldt/ga-tools
> https://github.com/mschuldt/ga144-sim
> > What I want to do is BUILD A DAMN BOARD.
> You have seen that one?
>
> https://hackaday.io/project/163652-ga144-evaluation-board
>
> --
> comp.lang.forth - Usenet's best soap opera?

Just to add this link I found
http://forth.org/svfig/kk/11-2015.html

On Sunday, 23 July 2023 at 08:10:10 UTC+1, Jurgen Pitaske wrote:
> On Sunday, 23 July 2023 at 06:10:24 UTC+1, yeti wrote:
> > Dave McGuire <mcg...@lssmuseum.org> writes:
> >
> > > Once again, the software is available. I didn't ask about that here
> > > because I found it already and have judged it to be sufficient for
> > > my needs.
> > Those?
> >
> > https://github.com/mschuldt/ga-tools
> > https://github.com/mschuldt/ga144-sim
> > > What I want to do is BUILD A DAMN BOARD.
> > You have seen that one?
> >
> > https://hackaday.io/project/163652-ga144-evaluation-board
> >
> > --
> > comp.lang.forth - Usenet's best soap opera?
> Just to add this link I found
> http://forth.org/svfig/kk/11-2015.html

And I had never seen this from 2017 - GA144 plus display
http://www.forth.org/svfig/kk/06-2017-Schuldt.pdf

On Sunday, 23 July 2023 at 08:20:49 UTC+1, Jurgen Pitaske wrote:
> On Sunday, 23 July 2023 at 08:10:10 UTC+1, Jurgen Pitaske wrote:
> > On Sunday, 23 July 2023 at 06:10:24 UTC+1, yeti wrote:
> > > Dave McGuire <mcg...@lssmuseum.org> writes:
> > >
> > > > Once again, the software is available. I didn't ask about that here
> > > > because I found it already and have judged it to be sufficient for
> > > > my needs.
> > > Those?
> > >
> > > https://github.com/mschuldt/ga-tools
> > > https://github.com/mschuldt/ga144-sim
> > > > What I want to do is BUILD A DAMN BOARD.
> > > You have seen that one?
> > >
> > > https://hackaday.io/project/163652-ga144-evaluation-board
> > >
> > > --
> > > comp.lang.forth - Usenet's best soap opera?
> > Just to add this link I found
> > http://forth.org/svfig/kk/11-2015.html
> And I had never seen this from 2017 - GA144 plus display
> http://www.forth.org/svfig/kk/06-2017-Schuldt.pdf

I had asked the question about board and circuit diagram in our Forth Facebook group, and here is a circuit diagram
http://esaid.free.fr/tutoriel_arrayforth/Ga144_pcb/Ga144/GA144_SRAM_IS2/GA144_SRAM_ISI2_schema.pdf

In article <u9csl3$56q$1@mail.neurotica.com>,
Dave McGuire <mcguire@lssmuseum.org> wrote:
>
> Is anyone aware of a simple development board for the GA144 chip? No
>fluff, extra processors, etc like the (expensive) GreenArrays GA144
>development boards, just the bare minimum to get the chip going and
>write code for it. Ideally an open design, i.e. download Gerber files
>and make a board or two. If there are none, I will probably design one
>myself but didn't want to reinvent the wheel.

I have some experience with using the actual development system
available from green arrays.
Before you spend time for the actual hardware, you can run an
emulator for the GA144. It is less effort, you can learn more of
the chip. If you are disappointed you can quit before investing
more time. See
https://bitbucket.org/lkonings/arrayfactor/downloads/
You can inspect the GA144 website, I'm not sure there is
an emulator and whether it is free.

On the hardware level, I applaud there being available a
development board. A modest goal is to use the "serdes"
protocol and run a single program on a border node.
That program is likely an assembler program.
The machine language is weird and the usual technique
to write an assembler don't work because of the multiple
instruction in a machine word.

The serdes protocol has to be reverse engineered.
Apparently for the purchasers of a development board the
source is somehow available ( dixit Leon Konings).
I recommend using a raspberry pico with noforth, because
it is more than likely the 10 io-processors are able
to do the serdes, once it is documented.

The pico noforth is available with the Dutch Forth User group.
https://forth.hcc.nl/
under products. We have a lot of products.

>
> Thanks,
> -Dave McGuire

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make spring.
You must not say "hey" before you have crossed the bridge. Don't sell the
hide of the bear until you shot it. Better one bird in the hand than ten in
the air. First gain is a cat spinning. - the Wise from Antrim -

In article <f27c8d93-b5cc-4840-9ce0-359869411b0fn@googlegroups.com>,
Lorem Ipsum <gnuarm.deletethisbit@gmail.com> wrote:
>On Saturday, July 22, 2023 at 10:23:07 AM UTC-4, Jurgen Pitaske wrote:
<SNIP>
>
>I asked about the memory interface, as I wanted to make it work with a
>fast DRAM (100-133 MHz). This would have required three internal nodes
>(minimum) and the use of the comms channels, of course. To run at full
>speed the DRAMs have to be timed carefully, so I needed timing data on
>the comms. They would not share that with me, claiming I could use it
>to reverse engineer the design. Really? You have a chip, no one is
>buying, but you are worried about people reverse engineering it?

This is worse than I thought.
This is reminiscint of ...
In the Dutch hcc a guy has a made
a brilliant composition (4 voice blues) for the time the Forth organ 1]
has 12 pipes, with a d'' .. d''' ranges with des missing.
He took it among him self to compose for this range, and use all
of the notes.
He doesn't allow a YouTube video of it to publish.

How to become unfamous, lesson 1.

1] now it has 24.

>It was built at a fab that specializes in old processes. I expect the
>process is still available.
It was old at the time. 180nm
Nowadays China are reporting break throughs at the 7nm and Taiwan is
routinely making 4 or 5 nm.
>
>If, by negativity, you mean relating facts that may be "inconvenient",
>then yes, that happens a lot here.
>
>> I would suggest you ceck with one of the Forth facebook groups.
>> There you can find probably more help and in a friendy way.
>> https://www.facebook.com/groups/PROGRAMMINGFORTH
>
>Just be careful which group you go with. Some are more friendly than
>others. A guy who goes by Peter Forth (not his real name) has banned
>several people from his group.

Peter Forth is extremely friendly towards the Dutch User group.
I declined an invitation to join because I don't like facebook.
How can he go under a false name? facebook requires a fotocopie
of your passport.

> Rick C.

Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make spring.
You must not say "hey" before you have crossed the bridge. Don't sell the
hide of the bear until you shot it. Better one bird in the hand than ten in
the air. First gain is a cat spinning. - the Wise from Antrim -

On Sunday, July 23, 2023 at 6:56:59 AM UTC-4, none albert wrote:
> In article <f27c8d93-b5cc-4840...@googlegroups.com>,
> Lorem Ipsum <gnuarm.del...@gmail.com> wrote:
> >On Saturday, July 22, 2023 at 10:23:07 AM UTC-4, Jurgen Pitaske wrote:
> <SNIP>
> >
> >I asked about the memory interface, as I wanted to make it work with a
> >fast DRAM (100-133 MHz). This would have required three internal nodes
> >(minimum) and the use of the comms channels, of course. To run at full
> >speed the DRAMs have to be timed carefully, so I needed timing data on
> >the comms. They would not share that with me, claiming I could use it
> >to reverse engineer the design. Really? You have a chip, no one is
> >buying, but you are worried about people reverse engineering it?
> This is worse than I thought.
> This is reminiscint of ...
> In the Dutch hcc a guy has a made
> a brilliant composition (4 voice blues) for the time the Forth organ 1]
> has 12 pipes, with a d'' .. d''' ranges with des missing.
> He took it among him self to compose for this range, and use all
> of the notes.
> He doesn't allow a YouTube video of it to publish.
>
> How to become unfamous, lesson 1.
>
> 1] now it has 24.
> >It was built at a fab that specializes in old processes. I expect the
> >process is still available.
> It was old at the time. 180nm
> Nowadays China are reporting break throughs at the 7nm and Taiwan is
> routinely making 4 or 5 nm.

Not sure what you are trying to say. It doesn't matter at all what anyone else is making. There are still many, many fabs making silicon in old processes. When a chip is designed, it is designed for a process. Moving it to another process is work. The many 20 year old chips, are not built on 4 nm fabs.

I wish I could remember the name of the company who built the GA144. Turns out, the number of wafers they built was in essence, the minimum quantity for the prototype run.

> >If, by negativity, you mean relating facts that may be "inconvenient",
> >then yes, that happens a lot here.
> >
> >> I would suggest you ceck with one of the Forth facebook groups.
> >> There you can find probably more help and in a friendy way.
> >> https://www.facebook.com/groups/PROGRAMMINGFORTH
> >
> >Just be careful which group you go with. Some are more friendly than
> >others. A guy who goes by Peter Forth (not his real name) has banned
> >several people from his group.
> Peter Forth is extremely friendly towards the Dutch User group.
> I declined an invitation to join because I don't like facebook.
> How can he go under a false name? facebook requires a fotocopie
> of your passport.

They don't require that specifically. They will treat your name as being verified if there is enough "evidence". I wanted a separate account from my personal one, so I signed up with a pseudonym. Peter ratted me out and Facebook blocked the account. I reported Peter's fake name and they accepted his name as "real" basically, because he has had it so long. Juergen says he found Peter's real name, so ask him how he found it.

If you think Peter Forth is a real name, try to find some evidence of it, other than on social media and such sites. If I am wrong, please correct me..

This is pretty off topic in this thread. I won't post about Peter further.

--

Rick C.

++- Get 1,000 miles of free Supercharging
++- Tesla referral code - https://ts.la/richard11209

On Sunday, 23 July 2023 at 19:28:56 UTC+1, Lorem Ipsum wrote:
> On Sunday, July 23, 2023 at 6:56:59 AM UTC-4, none albert wrote:
> > In article <f27c8d93-b5cc-4840...@googlegroups.com>,
> > Lorem Ipsum <gnuarm.del...@gmail.com> wrote:
> > >On Saturday, July 22, 2023 at 10:23:07 AM UTC-4, Jurgen Pitaske wrote:
> > <SNIP>
> > >
> > >I asked about the memory interface, as I wanted to make it work with a
> > >fast DRAM (100-133 MHz). This would have required three internal nodes
> > >(minimum) and the use of the comms channels, of course. To run at full
> > >speed the DRAMs have to be timed carefully, so I needed timing data on
> > >the comms. They would not share that with me, claiming I could use it
> > >to reverse engineer the design. Really? You have a chip, no one is
> > >buying, but you are worried about people reverse engineering it?
> > This is worse than I thought.
> > This is reminiscint of ...
> > In the Dutch hcc a guy has a made
> > a brilliant composition (4 voice blues) for the time the Forth organ 1]
> > has 12 pipes, with a d'' .. d''' ranges with des missing.
> > He took it among him self to compose for this range, and use all
> > of the notes.
> > He doesn't allow a YouTube video of it to publish.
> >
> > How to become unfamous, lesson 1.
> >
> > 1] now it has 24.
> > >It was built at a fab that specializes in old processes. I expect the
> > >process is still available.
> > It was old at the time. 180nm
> > Nowadays China are reporting break throughs at the 7nm and Taiwan is
> > routinely making 4 or 5 nm.
> Not sure what you are trying to say. It doesn't matter at all what anyone else is making. There are still many, many fabs making silicon in old processes. When a chip is designed, it is designed for a process. Moving it to another process is work. The many 20 year old chips, are not built on 4 nm fabs.
>
> I wish I could remember the name of the company who built the GA144. Turns out, the number of wafers they built was in essence, the minimum quantity for the prototype run.
> > >If, by negativity, you mean relating facts that may be "inconvenient",
> > >then yes, that happens a lot here.
> > >
> > >> I would suggest you ceck with one of the Forth facebook groups.
> > >> There you can find probably more help and in a friendy way.
> > >> https://www.facebook.com/groups/PROGRAMMINGFORTH
> > >
> > >Just be careful which group you go with. Some are more friendly than
> > >others. A guy who goes by Peter Forth (not his real name) has banned
> > >several people from his group.
> > Peter Forth is extremely friendly towards the Dutch User group.
> > I declined an invitation to join because I don't like facebook.
> > How can he go under a false name? facebook requires a fotocopie
> > of your passport.
> They don't require that specifically. They will treat your name as being verified if there is enough "evidence". I wanted a separate account from my personal one, so I signed up with a pseudonym. Peter ratted me out and Facebook blocked the account. I reported Peter's fake name and they accepted his name as "real" basically, because he has had it so long.

Juergen says he found Peter's real name, so ask him how he found it.
https://forth-ev.de/wiki/res/lib/exe/fetch.php/vd-archiv:4d2018-03.pdf
>
> If you think Peter Forth is a real name, try to find some evidence of it, other than on social media and such sites. If I am wrong, please correct me.
>
> This is pretty off topic in this thread. I won't post about Peter further..
>
> --
>
> Rick C.
>
> ++- Get 1,000 miles of free Supercharging
> ++- Tesla referral code - https://ts.la/richard11209

Peter Minuth - see here at the German Forth group, from 2018, page 8 and page 11
https://forth-ev.de/wiki/res/lib/exe/fetch.php/vd-archiv:4d2018-03.pdf
and confirmed by the German group then that this is Peter Forth

and see
https://comp.lang.forth.narkive.com/urZYOcu9/is-the-forth-language-under-the-control-of-mr-peter-forth

and as well
https://www.reddit.com/r/Forth/comments/zlxyel/peter_forths_toxic_behavior/

On Sunday, July 23, 2023 at 12:23:07 AM UTC+10, Jurgen Pitaske wrote:
> On Friday, 21 July 2023 at 04:05:11 UTC+1, Dave McGuire wrote:
> > Is anyone aware of a simple development board for the GA144 chip? No
> > fluff, extra processors, etc like the (expensive) GreenArrays GA144
> > development boards, just the bare minimum to get the chip going and
> > write code for it. Ideally an open design, i.e. download Gerber files
> > and make a board or two. If there are none, I will probably design one
> > myself but didn't want to reinvent the wheel.
> >
> > Thanks,
> > -Dave McGuire
> >
> > --
> > Dave McGuire, President/Curator
> > Large Scale Systems Museum
> > New Kensington, PA
> Thank you very much for leaving the link to your organisation.
> https://www.mact.io/about_us
>
> This theme GA144 has been discussed for probably 10 years here and in other places now.
>
> It is a shame, that no simple way for playing with these chips exists.
> They are very unusual, but the low interest probably demonstrates,
> that it is not really worth trying, except if you just want to for fun.
>
> Unfortunately the entry cost at Green Arrays is at least $200 for 10 chips - SMT unsoldered so you have to do all of the work.
> To my knowledge, there is not even a proven circuit diagram that you can use to build your own board.
> https://www.greenarraychips.com/home/products/index.php
>
> When I was more into Forth documentation,
> I asked Greg at Greenarrays, as I was very interested,
> if we could do a clean room implementation of a basic GA144 on FPGA - his feedback was extremely negative.
> So I gave up and did other things.
>
> I find it very unusual, that Chuck Moore is involved at GA,
> but seems not really to be pushing it either.
>
> To me it seems to be self limiting the sales,
> as they would run out of chips soon,
> and I wonder, if the fab who did these chips 10 to 15 years ago
> still exists now and could do more if needed..
>
> If you ask a question here on CLF,
> you have to be aware of the negativity that is quite normal here.
>
> I would suggest you ceck with one of the Forth facebook groups.
> There you can find probably more help and in a friendy way.
> https://www.facebook.com/groups/PROGRAMMINGFORTH
Well. It's hard to believe that after all this time, Google groups still
doesn't have a reply button for messages on mobile, or line splitting
by the looks of it.

Great to hear there are Facebook groups Jurgen. Thanks very much.
Maybe they can regulate the serial pests we get here.

Any Facebook groups good for forth processors?

Anyway, a question. Who runs this group? I would like to suggest to
them a: comp.lang.forth.hardware&processors group moderated, in that
you can ban certain accounts after a while. It would allow a lot of
forth hardware discussion in peace.

On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> Dave McGuire <mcg...@lssmuseum.org> writes:
>
> > Once again, the software is available. I didn't ask about that here
> > because I found it already and have judged it to be sufficient for
> > my needs.
> Those?
>
> https://github.com/mschuldt/ga-tools
> https://github.com/mschuldt/ga144-sim
> > What I want to do is BUILD A DAMN BOARD.
> You have seen that one?
>
> https://hackaday.io/project/163652-ga144-evaluation-board
>
> --
> comp.lang.forth - Usenet's best soap opera?

I was going recommend something like that. I just
couldn't remember where I saw it

It's a shame the processor was never given a performance accelerated
version and more memory, I could have used it. Even something like that
in the reduced core package with a lot of static memory on one
core (or shared by 4) with auto execution extended address bus. It
would have just enough pins to make it a nice little controller.

On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> > Dave McGuire <mcg...@lssmuseum.org> writes:
> >
> > > Once again, the software is available. I didn't ask about that here
> > > because I found it already and have judged it to be sufficient for
> > > my needs.
> > Those?
> >
> > https://github.com/mschuldt/ga-tools
> > https://github.com/mschuldt/ga144-sim
> > > What I want to do is BUILD A DAMN BOARD.
> > You have seen that one?
> >
> > https://hackaday.io/project/163652-ga144-evaluation-board
> >
> > --
> > comp.lang.forth - Usenet's best soap opera?
> I was going recommend something like that. I just
> couldn't remember where I saw it
>
> It's a shame the processor was never given a performance accelerated
> version and more memory, I could have used it.

Each processor has 700 MIPS! It's hard to use that level of performance as it is. Yes, memory is constrained... severely, but the real issue is the very hard to use comms. Each processor can only talk to it's neighbors and while they are passing data to another processor, they can't be doing *anything* else. So, each processor that needs data, is hanging up every other processor along the path. This was a feature that Chuck thought was "neat", but he never found a way to make use of it. He didn't even try until he had a chip to play with, spent sometime finding the comms to be a hard problem to solve, then retired.

> Even something like that
> in the reduced core package with a lot of static memory on one
> core (or shared by 4) with auto execution extended address bus. It
> would have just enough pins to make it a nice little controller.

If you hang static RAM on any version of a GAxxx processor, the power consumption goes through the roof (static RAM is very power hungry) and you still can't get information to the processors fast enough because of the poor comms. Maybe, if these issues had been considered during the design of the chip, something could have been done.

Accessing the CPU memory already takes multiple instruction times. Adding more memory to the processors will slow them down further. The GA144 is such a queer chip.

--

Rick C.

+++ Get 1,000 miles of free Supercharging
+++ Tesla referral code - https://ts.la/richard11209

S <waynemorellini@gmail.com> writes:

> Any Facebook groups good for forth processors?
>
> Anyway, a question. Who runs this group? I would like to suggest to
> them a: comp.lang.forth.hardware&processors group moderated, in that
> you can ban certain accounts after a while. It would allow a lot of
> forth hardware discussion in peace.

I prefer to read all that stuff here.

--
Take Back Control! -- Mesh The Planet!
I do not play Nethack, I do play GNUS! o;-)
Solid facts do not need 1001 pictures.

On Sunday, July 23, 2023 at 11:49:05 AM UTC+10, Dave McGuire wrote:
> On 7/22/23 15:01, Lorem Ipsum wrote:
> >> I would suggest you ceck with one of the Forth facebook groups.
> >> There you can find probably more help and in a friendy way.
> >> https://www.facebook.com/groups/PROGRAMMINGFORTH
> >
> > Just be careful which group you go with. Some are more friendly than others. A guy who goes by Peter Forth (not his real name) has banned several people from his group.
> Interesting! Peter Forth (whatever his real name may be) has never
> been anything other than nice and friendly to me, where YOU have never
> been anything other than a dick.
>
> Every newsgroup has their armchair expert, wannabe authority troll.
> I'm glad I found this one's early before making any friends here.
>
> *PLONK*
>
> -Dave
> --
> Dave McGuire, President/Curator
> Large Scale Systems Museum
> New Kensington, PA

I could have saved you the effort. Certain people here seem to
like to contribute long repetitious useless conversations where
they don't seem to understand l. This tends to happen when
useful people turn up with something worth saying about forth
hardware. Really hermetic passive aggressive controlling
wrecking behaviour. There is a poor chap here who makes
candles now, who really used to cop it. He might have got a bit
excited, but I'm more interested in investing in people than being
a real .ick.

Rick, on the other hand, does some real interesting hardware for
the military. It's a shame he doesn't put his talents to good use
making a chip that is an alternative to the GA144 he complains
about. Maybe he will get more respect he wants. I have a friend
who, if he is not the centre or attention and what he wants to talk
about, and perceives he is not getting the level of submissive
respect he thinks he deserves, gets snippy, and dominates and talks
over you, disrupts and pulls all sorts of stunts. I've actually got two
friends a bit like that. The other one is better, not so self centred, a
Christian. Both could be in show business. Me too, but I've had lots
of physical sickness but similar sort of energy, but with a brain
together. That's why I attract those sorts.

Now, Rick likes to claim a lot of knowledge, but he's been stuck in
military contracts, which have very little to do with products for 100's
of thousands to thousands times more volume in consumer markets.
It's really gravy train profits decisions compared to razor thin margin
Innovation and strategy. He has opinions, but all the top people are curious
explorers rather than people want to stay put. So, do what you like
Dave. Don't let yourself be running the reservation.

I'm going to say a few things. I've been long looking into how to
fabricate chip alternatives from home (garage setup) and have finally
realised a low tech version, which I would expect to be able to do 1 micro
circuits of, relativity, high performance for 1 micron. I can theoretically go to
1nm but that would be a lot harder and more difficult to clean room. I tend to
Keep things reasonable practical doable. I am still undergoing a lot of stuff
here, and after vaccine and long covid reactions last year, could have died..
But, I managed to find out about some things that corrected that a lot. I now
can't do maths muc and still have some other deficits. Plus, there is an
ongoing dispute, where I was very mistreated, and badly done by. So, I won't be
able to work on it for a while. However.

Jurgen has a book on Dr Ting's forth array design (thanks for the book Jurgen,
still haven't got around to it) and Jeff Fox, was doing an earlier misc processor
with on chip IO video etc, the F21 and software GUI and OS, and his widow might
have the rights to the design. He told me he was also planning parallel arrays up
to 10,000 chips on wafer. So, he might have some sort of pre Seaforth parallel design
work there as well. So, I encourage you to look at something like that as well.

Have a good day

Wayne.

On Sunday, July 23, 2023 at 11:49:05 AM UTC+10, Dave McGuire wrote:
> On 7/22/23 15:01, Lorem Ipsum wrote:
> >> I would suggest you ceck with one of the Forth facebook groups.
> >> There you can find probably more help and in a friendy way.
> >> https://www.facebook.com/groups/PROGRAMMINGFORTH
> >
> > Just be careful which group you go with. Some are more friendly than others. A guy who goes by Peter Forth (not his real name) has banned several people from his group.
> Interesting! Peter Forth (whatever his real name may be) has never
> been anything other than nice and friendly to me, where YOU have never
> been anything other than a dick.
>
> Every newsgroup has their armchair expert, wannabe authority troll.
> I'm glad I found this one's early before making any friends here.
>
> *PLONK*
>
> -Dave
> --
> Dave McGuire, President/Curator
> Large Scale Systems Museum
> New Kensington, PA

I could have saved you the effort. Certain people here seem to
like to contribute long repetitious useless conversations where
they don't seem to understand l. This tends to happen when
useful people turn up with something worth saying about forth
hardware. Really hermetic passive aggressive controlling
wrecking behaviour. There is a poor chap here who makes
candles now, who really used to cop it. He might have got a bit
excited, but I'm more interested in investing in people than being
a real .ick.

Rick, on the other hand, does some real interesting hardware for
the military. It's a shame he doesn't put his talents to good use
making a chip that is an alternative to the GA144 he complains
about. Maybe he will get more respect he wants. I have a friend
who, if he is not the centre or attention and what he wants to talk
about, and perceives he is not getting the level of submissive
respect he thinks he deserves, gets snippy, and dominates and talks
over you, disrupts and pulls all sorts of stunts. I've actually got two
friends a bit like that. The other one is better, not so self centred, a
Christian. Both could be in show business. Me too, but I've had lots
of physical sickness but similar sort of energy, but with a brain
together. That's why I attract those sorts.

Now, Rick likes to claim a lot of knowledge, but he's been stuck in
military contracts, which have very little to do with products for 100's
of thousands to thousands times more volume in consumer markets.
It's really gravy train profits decisions compared to razor thin margin
Innovation and strategy. He has opinions, but all the top people are curious
explorers rather than people want to stay put. So, do what you like
Dave. Don't let yourself be running the reservation.

I'm going to say a few things. I've been long looking into how to
fabricate chip alternatives from home (garage setup) and have finally
realised a low tech version, which I would expect to be able to do 1 micro
circuits of, relativity, high performance for 1 micron. I can theoretically go to
1nm but that would be a lot harder and more difficult to clean room. I tend to
Keep things reasonable practical doable. I am still undergoing a lot of stuff
here, and after vaccine and long covid reactions last year, could have died..
But, I managed to find out about some things that corrected that a lot. I now
can't do maths muc and still have some other deficits. Plus, there is an
ongoing dispute, where I was very mistreated, and badly done by. So, I won't be
able to work on it for a while. However.

Jurgen has a book on Dr Ting's forth array design (thanks for the book Jurgen,
still haven't got around to it) and Jeff Fox, was doing an earlier misc processor
with on chip IO video etc, the F21 and software GUI and OS, and his widow might
have the rights to the design. He told me he was also planning parallel arrays up
to 10,000 chips on wafer. So, he might have some sort of pre Seaforth parallel design
work there as well. So, I encourage you to look at something like that as well.

Have a good day

Wayne.

On Tuesday, August 22, 2023 at 3:41:50 AM UTC+10, Lorem Ipsum wrote:
> On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> > On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> > > Dave McGuire <mcg...@lssmuseum.org> writes:

...

> > It's a shame the processor was never given a performance accelerated
> > version and more memory, I could have used it.

I did say performance version, which would have all this stuff sorted out.
My design proposal for this a decade to trot decades ago, sorted this all out.
Hardly any stalling, no pressor IO cycle consumption, large memory direct
addressing and execution space, and large shared memory and large memory for
controlling core, and any core designed so, sizable shared up to 8 core transaction data memories, with three levels of bus, two shared, with minimal footprint, plus mini cache
and DMA design, which can work in any of the shared memories. Designed to
distribute tasks and memory usage in a way that easily maximize performance.. Plus
a few other things back in the early proposal. Answers most of the questions, but I
would also add a serial pseudo SRAM to parallel bus auto circuit, to decode data and execution as if a normal parallel bus, but at lower speed of course. Once you add the
mini cache and page swap features, and core can access the external memory to dma
In the next instruction or word or up to the whole local memory. All these mini features
are low resistor count versions of less performance compared to traditional, but simple
to use and judicially used to get the programmer out of a jam. I was listening when Chuck
Complained about the normal size of these features, so I designed the proposals, not to
sacrifice much chip real-estate. I'm taking about hundreds of transistors. I can't
remember the seperate estimates, but it's small, but design ex to greatly boost throughout. Plus you could run the chip down to 1ns to 2/10th of a nanosecond, on a better node process.
High performance.

> Each processor has 700 MIPS! It's hard to use that level of performance as it is. Yes, memory is constrained... severely, but the real issue is the very hard to use comms. Each processor can only talk to it's neighbors and while they are passing data to another processor, they can't be doing *anything* else. So, each processor that needs data, is hanging up every other processor along the path. This was a feature that Chuck thought was "neat", but he never found a way to make use of it. He didn't even try until he had a chip to play with, spent sometime finding the comms to be a hard problem to solve, then retired.

With the proposed design, it still can operate asynchronously. So, it can operate at 20hz if it wanted to, without complex programming.

> > Even something like that
> > in the reduced core package with a lot of static memory on one
> > core (or shared by 4) with auto execution extended address bus. It
> > would have just enough pins to make it a nice little controller.
> If you hang static RAM on any version of a GAxxx processor, the power consumption goes through the roof (static RAM is very power hungry) and you still can't get information to the processors fast enough because of the poor comms. Maybe, if these issues had been considered during the design of the chip, something could have been done.

I didn't say how much, but it would be considerable. At least as much as in the whole current
chip, up to a full 18 bits. The present chip seemed to do fine with static memory. However
it would be good with the full account of the present cores memory spaces for execution ram rom and data. Going one more step the ability to insert an parallel psram die in package, rather than just use SRAM. Cheap in quantity. This allow the same die to be packed with
varying amounts of memory and number of memories, depending on the application. A lot cheaper than using a specialist memory incorporating process node or high transit count
SRAM. With this the psram due can be whatever process node sized dram inside for commodity like mass production like pricing advantage available, while the main chip can
remain at 130-180nm.

>
> Accessing the CPU memory already takes multiple instruction times. Adding more memory to the processors will slow them down further. The GA144 is such a queer chip.
>
>
> Rick C.
>
> +++ Get 1,000 miles of free Supercharging
> +++ Tesla referral code - https://ts.la/richard11209

On Tuesday, August 22, 2023 at 3:41:50 AM UTC+10, Lorem Ipsum wrote:
> On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> > On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> > > Dave McGuire <mcg...@lssmuseum.org> writes:

...

> > It's a shame the processor was never given a performance accelerated
> > version and more memory, I could have used it.

I did say performance version, which would have all this stuff sorted out.
My design proposal for this a decade to trot decades ago, sorted this all out.
Hardly any stalling, no pressor IO cycle consumption, large memory direct
addressing and execution space, and large shared memory and large memory for
controlling core, and any core designed so, sizable shared up to 8 core transaction data memories, with three levels of bus, two shared, with minimal footprint, plus mini cache
and DMA design, which can work in any of the shared memories. Designed to
distribute tasks and memory usage in a way that easily maximize performance.. Plus
a few other things back in the early proposal. Answers most of the questions, but I
would also add a serial pseudo SRAM to parallel bus auto circuit, to decode data and execution as if a normal parallel bus, but at lower speed of course. Once you add the
mini cache and page swap features, and core can access the external memory to dma
In the next instruction or word or up to the whole local memory. All these mini features
are low resistor count versions of less performance compared to traditional, but simple
to use and judicially used to get the programmer out of a jam. I was listening when Chuck
Complained about the normal size of these features, so I designed the proposals, not to
sacrifice much chip real-estate. I'm taking about hundreds of transistors. I can't
remember the seperate estimates, but it's small, but design ex to greatly boost throughout. Plus you could run the chip down to 1ns to 2/10th of a nanosecond, on a better node process.
High performance.

> Each processor has 700 MIPS! It's hard to use that level of performance as it is. Yes, memory is constrained... severely, but the real issue is the very hard to use comms. Each processor can only talk to it's neighbors and while they are passing data to another processor, they can't be doing *anything* else. So, each processor that needs data, is hanging up every other processor along the path. This was a feature that Chuck thought was "neat", but he never found a way to make use of it. He didn't even try until he had a chip to play with, spent sometime finding the comms to be a hard problem to solve, then retired.

With the proposed design, it still can operate asynchronously. So, it can operate at 20hz if it wanted to, without complex programming.

> > Even something like that
> > in the reduced core package with a lot of static memory on one
> > core (or shared by 4) with auto execution extended address bus. It
> > would have just enough pins to make it a nice little controller.
> If you hang static RAM on any version of a GAxxx processor, the power consumption goes through the roof (static RAM is very power hungry) and you still can't get information to the processors fast enough because of the poor comms. Maybe, if these issues had been considered during the design of the chip, something could have been done.

I didn't say how much, but it would be considerable. At least as much as in the whole current
chip, up to a full 18 bits. The present chip seemed to do fine with static memory. However
it would be good with the full account of the present cores memory spaces for execution ram rom and data. Going one more step the ability to insert an parallel psram die in package, rather than just use SRAM. Cheap in quantity. This allow the same die to be packed with
varying amounts of memory and number of memories, depending on the application. A lot cheaper than using a specialist memory incorporating process node or high transit count
SRAM. With this the psram due can be whatever process node sized dram inside for commodity like mass production like pricing advantage available, while the main chip can
remain at 130-180nm.

>
> Accessing the CPU memory already takes multiple instruction times. Adding more memory to the processors will slow them down further. The GA144 is such a queer chip.
>
>
> Rick C.
>
> +++ Get 1,000 miles of free Supercharging
> +++ Tesla referral code - https://ts.la/richard11209

On Monday, August 21, 2023 at 3:02:58 PM UTC-4, S wrote:
> On Tuesday, August 22, 2023 at 3:41:50 AM UTC+10, Lorem Ipsum wrote:
> > On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> > > On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> > > > Dave McGuire <mcg...@lssmuseum.org> writes:
> ..
> > > It's a shame the processor was never given a performance accelerated
> > > version and more memory, I could have used it.
> I did say performance version, which would have all this stuff sorted out..

So, you waved your magic wand over the GA144 and solved all the problems? Great! Show us how you did that.

> My design proposal for this a decade to trot decades ago, sorted this all out.
> Hardly any stalling, no pressor IO cycle consumption, large memory direct
> addressing and execution space, and large shared memory and large memory for
> controlling core, and any core designed so, sizable shared up to 8 core transaction data memories, with three levels of bus, two shared, with minimal footprint, plus mini cache
> and DMA design, which can work in any of the shared memories. Designed to
> distribute tasks and memory usage in a way that easily maximize performance. Plus
> a few other things back in the early proposal. Answers most of the questions, but I
> would also add a serial pseudo SRAM to parallel bus auto circuit, to decode data and execution as if a normal parallel bus, but at lower speed of course. Once you add the
> mini cache and page swap features, and core can access the external memory to dma
> In the next instruction or word or up to the whole local memory. All these mini features
> are low resistor count versions of less performance compared to traditional, but simple
> to use and judicially used to get the programmer out of a jam. I was listening when Chuck
> Complained about the normal size of these features, so I designed the proposals, not to
> sacrifice much chip real-estate. I'm taking about hundreds of transistors.. I can't
> remember the seperate estimates, but it's small, but design ex to greatly boost throughout. Plus you could run the chip down to 1ns to 2/10th of a nanosecond, on a better node process.
> High performance.

The only problem is, you've done none of this. But when you do, let us know. I'm sure it will be very interesting.

> > Each processor has 700 MIPS! It's hard to use that level of performance as it is. Yes, memory is constrained... severely, but the real issue is the very hard to use comms. Each processor can only talk to it's neighbors and while they are passing data to another processor, they can't be doing *anything* else. So, each processor that needs data, is hanging up every other processor along the path. This was a feature that Chuck thought was "neat", but he never found a way to make use of it. He didn't even try until he had a chip to play with, spent sometime finding the comms to be a hard problem to solve, then retired.
> With the proposed design, it still can operate asynchronously. So, it can operate at 20hz if it wanted to, without complex programming.

Your comment seems to be unrelated to what it follows. What point are you trying to make???

> > > Even something like that
> > > in the reduced core package with a lot of static memory on one
> > > core (or shared by 4) with auto execution extended address bus. It
> > > would have just enough pins to make it a nice little controller.
> > If you hang static RAM on any version of a GAxxx processor, the power consumption goes through the roof (static RAM is very power hungry) and you still can't get information to the processors fast enough because of the poor comms. Maybe, if these issues had been considered during the design of the chip, something could have been done.
> I didn't say how much, but it would be considerable. At least as much as in the whole current
> chip, up to a full 18 bits. The present chip seemed to do fine with static memory. However
> it would be good with the full account of the present cores memory spaces for execution ram rom and data. Going one more step the ability to insert an parallel psram die in package, rather than just use SRAM. Cheap in quantity. This allow the same die to be packed with
> varying amounts of memory and number of memories, depending on the application. A lot cheaper than using a specialist memory incorporating process node or high transit count
> SRAM. With this the psram due can be whatever process node sized dram inside for commodity like mass production like pricing advantage available, while the main chip can
> remain at 130-180nm.

It's just that there's no point in adding memory until you can do something useful with it.

I remember you now. You are the guy who blamed everyone else for replying to your posts, making it impossible for you to do any work until you replied in kind. That's a pretty severe distraction disorder. I wish you luck with it.

--

Rick C.

---- Get 1,000 miles of free Supercharging
---- Tesla referral code - https://ts.la/richard11209

In article <cefeb263-b1ed-4961-b1ef-e09840212a2en@googlegroups.com>,
Lorem Ipsum <gnuarm.deletethisbit@gmail.com> wrote:
>On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
>> On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
>> > Dave McGuire <mcg...@lssmuseum.org> writes:
>> >
>> > > Once again, the software is available. I didn't ask about that here
>> > > because I found it already and have judged it to be sufficient for
>> > > my needs.
>> > Those?
>> >
>> > https://github.com/mschuldt/ga-tools
>> > https://github.com/mschuldt/ga144-sim
>> > > What I want to do is BUILD A DAMN BOARD.
>> > You have seen that one?
>> >
>> > https://hackaday.io/project/163652-ga144-evaluation-board
>> >
>> > --
>> > comp.lang.forth - Usenet's best soap opera?
>> I was going recommend something like that. I just
>> couldn't remember where I saw it
>>
>> It's a shame the processor was never given a performance accelerated
>> version and more memory, I could have used it.
>
>Each processor has 700 MIPS! It's hard to use that level of performance
>as it is. Yes, memory is constrained... severely, but the real issue is
>the very hard to use comms. Each processor can only talk to it's
>neighbors and while they are passing data to another processor, they
>can't be doing *anything* else. So, each processor that needs data, is
>hanging up every other processor along the path. This was a feature
>that Chuck thought was "neat", but he never found a way to make use of
>it. He didn't even try until he had a chip to play with, spent sometime
>finding the comms to be a hard problem to solve, then retired.

The GA144 cannot have path that are crossing each other.
That is a fatal design flaw.
>
>
>> Even something like that
>> in the reduced core package with a lot of static memory on one
>> core (or shared by 4) with auto execution extended address bus. It
>> would have just enough pins to make it a nice little controller.
>
>If you hang static RAM on any version of a GAxxx processor, the power
>consumption goes through the roof (static RAM is very power hungry) and
>you still can't get information to the processors fast enough because of
>the poor comms. Maybe, if these issues had been considered during the
>design of the chip, something could have been done.

I thought of hanging a 32 bit static memory using the weird timig.
Then you have parallel stack to emulate a 32 bit Forth machine.
It is climbing the Mount Everest, infinitely difficult and
infinitely useless.

>
>Accessing the CPU memory already takes multiple instruction times.
>Adding more memory to the processors will slow them down further. The
>GA144 is such a queer chip.
Agreed.
> Rick C.
Groetjes Albert
--
Don't praise the day before the evening. One swallow doesn't make spring.
You must not say "hey" before you have crossed the bridge. Don't sell the
hide of the bear until you shot it. Better one bird in the hand than ten in
the air. First gain is a cat spinning. - the Wise from Antrim -

On Tuesday, August 22, 2023 at 5:16:02 AM UTC+10, Lorem Ipsum wrote:
> On Monday, August 21, 2023 at 3:02:58 PM UTC-4, S wrote:
> > On Tuesday, August 22, 2023 at 3:41:50 AM UTC+10, Lorem Ipsum wrote:
> > > On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> > > > On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> > > > > Dave McGuire <mcg...@lssmuseum.org> writes:
> > ..
> > > > It's a shame the processor was never given a performance accelerated
> > > > version and more memory, I could have used it.
> > I did say performance version, which would have all this stuff sorted out.
> So, you waved your magic wand over the GA144 and solved all the problems? Great! Show us how you did that.

You are paying any of us, or for patents. It's simple enough, give it a go yourself (or at least try to look up the posts I put some of it in 20 years ago).

> > My design proposal for this a decade to trot decades ago, sorted this all out.
> > Hardly any stalling, no pressor IO cycle consumption, large memory direct
> > addressing and execution space, and large shared memory and large memory for
> > controlling core, and any core designed so, sizable shared up to 8 core transaction data memories, with three levels of bus, two shared, with minimal footprint, plus mini cache
> > and DMA design, which can work in any of the shared memories. Designed to
> > distribute tasks and memory usage in a way that easily maximize performance. Plus
> > a few other things back in the early proposal. Answers most of the questions, but I
> > would also add a serial pseudo SRAM to parallel bus auto circuit, to decode data and execution as if a normal parallel bus, but at lower speed of course. Once you add the
> > mini cache and page swap features, and core can access the external memory to dma
> > In the next instruction or word or up to the whole local memory. All these mini features
> > are low resistor count versions of less performance compared to traditional, but simple
> > to use and judicially used to get the programmer out of a jam. I was listening when Chuck
> > Complained about the normal size of these features, so I designed the proposals, not to
> > sacrifice much chip real-estate. I'm taking about hundreds of transistors. I can't
> > remember the seperate estimates, but it's small, but design ex to greatly boost throughout. Plus you could run the chip down to 1ns to 2/10th of a nanosecond, on a better node process.
> > High performance.
> The only problem is, you've done none of this. But when you do, let us know. I'm sure it will be very interesting.

The problem is, at least I figured out the logical architecture before I said anything.

> > > Each processor has 700 MIPS! It's hard to use that level of performance as it is. Yes, memory is constrained... severely, but the real issue is the very hard to use comms. Each processor can only talk to it's neighbors and while they are passing data to another processor, they can't be doing *anything* else. So, each processor that needs data, is hanging up every other processor along the path. This was a feature that Chuck thought was "neat", but he never found a way to make use of it. He didn't even try until he had a chip to play with, spent sometime finding the comms to be a hard problem to solve, then retired.
> > With the proposed design, it still can operate asynchronously. So, it can operate at 20hz if it wanted to, without complex programming.
> Your comment seems to be unrelated to what it follows. What point are you trying to make???

That you don't have to try to use 700mips, and every cycle you use is more or less an minimal on actual work/communications, compared to everything both of us complain about in performance and programmability.

> > > > Even something like that
> > > > in the reduced core package with a lot of static memory on one
> > > > core (or shared by 4) with auto execution extended address bus. It
> > > > would have just enough pins to make it a nice little controller.
> > > If you hang static RAM on any version of a GAxxx processor, the power consumption goes through the roof (static RAM is very power hungry) and you still can't get information to the processors fast enough because of the poor comms. Maybe, if these issues had been considered during the design of the chip, something could have been done.
> > I didn't say how much, but it would be considerable. At least as much as in the whole current
> > chip, up to a full 18 bits. The present chip seemed to do fine with static memory. However
> > it would be good with the full account of the present cores memory spaces for execution ram rom and data. Going one more step the ability to insert an parallel psram die in package, rather than just use SRAM. Cheap in quantity. This allow the same die to be packed with
> > varying amounts of memory and number of memories, depending on the application. A lot cheaper than using a specialist memory incorporating process node or high transit count
> > SRAM. With this the psram due can be whatever process node sized dram inside for commodity like mass production like pricing advantage available, while the main chip can
> > remain at 130-180nm.
> It's just that there's no point in adding memory until you can do something useful with it. Well you can't like any processor. It's direct addressable direct executable. Same as a microwave controller with on chip memory.
>
> I remember you now. You are the guy who blamed everyone else for replying to your posts, making it impossible for you to do any work until you replied in kind. That's a pretty severe distraction disorder. I wish you luck with it.

No, it's mainly just a few people pestering. You can't run investment or community projects with, pestering trying to deliberately distract people from it with pointless stuff, to shade and colour things. Well, three interruptions rather than over ten I would have normally have expected for that amount of text. But, you can see a few changes on misc would get rid of most of the concerns. It's just a shame that everything is too expensive to move onto a faster process with lower energy design, for all of us. The costs are nuts now. I really would like to see a latest serial bus user as a standard to communicate between all devices daisy chained, off a chip package with very few pads and supporting USB device protocols. Simplify costs and everything off chip, and who cares if the CPU is only low-cost 130-180nm..

>
> --
>
> Rick C.

> ---- Get 1,000 miles of free Supercharging
> ---- Tesla referral code - https://ts.la/richard11209

On Tuesday, August 22, 2023 at 3:57:06 AM UTC-4, none albert wrote:
> In article <cefeb263-b1ed-4961...@googlegroups.com>,
> Lorem Ipsum <gnuarm.del...@gmail.com> wrote:
> >On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> >> On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> >> > Dave McGuire <mcg...@lssmuseum.org> writes:
> >> >
> >> > > Once again, the software is available. I didn't ask about that here
> >> > > because I found it already and have judged it to be sufficient for
> >> > > my needs.
> >> > Those?
> >> >
> >> > https://github.com/mschuldt/ga-tools
> >> > https://github.com/mschuldt/ga144-sim
> >> > > What I want to do is BUILD A DAMN BOARD.
> >> > You have seen that one?
> >> >
> >> > https://hackaday.io/project/163652-ga144-evaluation-board
> >> >
> >> > --
> >> > comp.lang.forth - Usenet's best soap opera?
> >> I was going recommend something like that. I just
> >> couldn't remember where I saw it
> >>
> >> It's a shame the processor was never given a performance accelerated
> >> version and more memory, I could have used it.
> >
> >Each processor has 700 MIPS! It's hard to use that level of performance
> >as it is. Yes, memory is constrained... severely, but the real issue is
> >the very hard to use comms. Each processor can only talk to it's
> >neighbors and while they are passing data to another processor, they
> >can't be doing *anything* else. So, each processor that needs data, is
> >hanging up every other processor along the path. This was a feature
> >that Chuck thought was "neat", but he never found a way to make use of
> >it. He didn't even try until he had a chip to play with, spent sometime
> >finding the comms to be a hard problem to solve, then retired.
> The GA144 cannot have path that are crossing each other.
> That is a fatal design flaw.

I don't believe it is true that data paths can not cross. They just become much slower data paths, since they essentially need to be polled. In fact, I don't believe you can have any two data paths through a node without using polling to detect when a sample is waiting for you to pick it up and move it.

> >> Even something like that
> >> in the reduced core package with a lot of static memory on one
> >> core (or shared by 4) with auto execution extended address bus. It
> >> would have just enough pins to make it a nice little controller.
> >
> >If you hang static RAM on any version of a GAxxx processor, the power
> >consumption goes through the roof (static RAM is very power hungry) and
> >you still can't get information to the processors fast enough because of
> >the poor comms. Maybe, if these issues had been considered during the
> >design of the chip, something could have been done.
> I thought of hanging a 32 bit static memory using the weird timig.
> Then you have parallel stack to emulate a 32 bit Forth machine.
> It is climbing the Mount Everest, infinitely difficult and
> infinitely useless.

I don't know what you mean about "weird timing". Static RAM has pretty simple timing. It gets a bit tricky to meet all the specs if you are trying to run as fast as possible, but the GA144 doesn't specify the timing on the internal paths you need to make this work. That was when I gave up. The person I contacted at GA refused to provide the info because of "trade secrets".

> >Accessing the CPU memory already takes multiple instruction times.
> >Adding more memory to the processors will slow them down further. The
> >GA144 is such a queer chip.
> Agreed.

Someone described the chip as Moore's toy. It took me a while to realize this is correct. It was simply a bunch of ideas thrown into one chip, without any real thought of how to use them.

--

Rick C.

----+ Get 1,000 miles of free Supercharging
----+ Tesla referral code - https://ts.la/richard11209

On Tuesday, August 22, 2023 at 3:57:33 AM UTC-4, S wrote:
> On Tuesday, August 22, 2023 at 5:16:02 AM UTC+10, Lorem Ipsum wrote:
> > On Monday, August 21, 2023 at 3:02:58 PM UTC-4, S wrote:
> > > On Tuesday, August 22, 2023 at 3:41:50 AM UTC+10, Lorem Ipsum wrote:
> > > > On Monday, August 21, 2023 at 1:04:38 PM UTC-4, S wrote:
> > > > > On Sunday, July 23, 2023 at 3:10:24 PM UTC+10, yeti wrote:
> > > > > > Dave McGuire <mcg...@lssmuseum.org> writes:
> > > ..
> > > > > It's a shame the processor was never given a performance accelerated
> > > > > version and more memory, I could have used it.
> > > I did say performance version, which would have all this stuff sorted out.
> > So, you waved your magic wand over the GA144 and solved all the problems? Great! Show us how you did that.
> You are paying any of us, or for patents. It's simple enough, give it a go yourself (or at least try to look up the posts I put some of it in 20 years ago).

That's what I thought. You talk big, but actually have no idea.

> > > My design proposal for this a decade to trot decades ago, sorted this all out.
> > > Hardly any stalling, no pressor IO cycle consumption, large memory direct
> > > addressing and execution space, and large shared memory and large memory for
> > > controlling core, and any core designed so, sizable shared up to 8 core transaction data memories, with three levels of bus, two shared, with minimal footprint, plus mini cache
> > > and DMA design, which can work in any of the shared memories. Designed to
> > > distribute tasks and memory usage in a way that easily maximize performance. Plus
> > > a few other things back in the early proposal. Answers most of the questions, but I
> > > would also add a serial pseudo SRAM to parallel bus auto circuit, to decode data and execution as if a normal parallel bus, but at lower speed of course. Once you add the
> > > mini cache and page swap features, and core can access the external memory to dma
> > > In the next instruction or word or up to the whole local memory. All these mini features
> > > are low resistor count versions of less performance compared to traditional, but simple
> > > to use and judicially used to get the programmer out of a jam. I was listening when Chuck
> > > Complained about the normal size of these features, so I designed the proposals, not to
> > > sacrifice much chip real-estate. I'm taking about hundreds of transistors. I can't
> > > remember the seperate estimates, but it's small, but design ex to greatly boost throughout. Plus you could run the chip down to 1ns to 2/10th of a nanosecond, on a better node process.
> > > High performance.
> > The only problem is, you've done none of this. But when you do, let us know. I'm sure it will be very interesting.
> The problem is, at least I figured out the logical architecture before I said anything.

Sure, you have it all figured out. Good for you. Too bad you can't explain any of it.

> > > > Each processor has 700 MIPS! It's hard to use that level of performance as it is. Yes, memory is constrained... severely, but the real issue is the very hard to use comms. Each processor can only talk to it's neighbors and while they are passing data to another processor, they can't be doing *anything* else. So, each processor that needs data, is hanging up every other processor along the path. This was a feature that Chuck thought was "neat", but he never found a way to make use of it. He didn't even try until he had a chip to play with, spent sometime finding the comms to be a hard problem to solve, then retired.
> > > With the proposed design, it still can operate asynchronously. So, it can operate at 20hz if it wanted to, without complex programming.
> > Your comment seems to be unrelated to what it follows. What point are you trying to make???
> That you don't have to try to use 700mips, and every cycle you use is more or less an minimal on actual work/communications, compared to everything both of us complain about in performance and programmability.

Of course not. But you are talking about making the processors an order of magnitude faster, when the current speed can't be tapped. Why not try to solve the problems the chip actually has, before solving problems it doesn't have?

> > > > > Even something like that
> > > > > in the reduced core package with a lot of static memory on one
> > > > > core (or shared by 4) with auto execution extended address bus. It
> > > > > would have just enough pins to make it a nice little controller.
> > > > If you hang static RAM on any version of a GAxxx processor, the power consumption goes through the roof (static RAM is very power hungry) and you still can't get information to the processors fast enough because of the poor comms. Maybe, if these issues had been considered during the design of the chip, something could have been done.
> > > I didn't say how much, but it would be considerable. At least as much as in the whole current
> > > chip, up to a full 18 bits. The present chip seemed to do fine with static memory. However
> > > it would be good with the full account of the present cores memory spaces for execution ram rom and data. Going one more step the ability to insert an parallel psram die in package, rather than just use SRAM. Cheap in quantity. This allow the same die to be packed with
> > > varying amounts of memory and number of memories, depending on the application. A lot cheaper than using a specialist memory incorporating process node or high transit count
> > > SRAM. With this the psram due can be whatever process node sized dram inside for commodity like mass production like pricing advantage available, while the main chip can
> > > remain at 130-180nm.
> > It's just that there's no point in adding memory until you can do something useful with it. Well you can't like any processor. It's direct addressable direct executable. Same as a microwave controller with on chip memory.
> >
> > I remember you now. You are the guy who blamed everyone else for replying to your posts, making it impossible for you to do any work until you replied in kind. That's a pretty severe distraction disorder. I wish you luck with it.
> No, it's mainly just a few people pestering. You can't run investment or community projects with, pestering trying to deliberately distract people from it with pointless stuff, to shade and colour things.

If you can't direct your attention to the things you want to get done, no, you will never get anywhere. Focus is 100% your issue, no one else's.

> Well, three interruptions rather than over ten I would have normally have expected for that amount of text. But, you can see a few changes on misc would get rid of most of the concerns. It's just a shame that everything is too expensive to move onto a faster process with lower energy design, for all of us. The costs are nuts now. I really would like to see a latest serial bus user as a standard to communicate between all devices daisy chained, off a chip package with very few pads and supporting USB device protocols. Simplify costs and everything off chip, and who cares if the CPU is only low-cost 130-180nm.

Exactly! Who cares?

--

Rick C.

---+- Get 1,000 miles of free Supercharging
---+- Tesla referral code - https://ts.la/richard11209